cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
261 Views
Registered: ‎11-02-2019

Ultra96-V2 constraints error

Hi!

I want to try the Ultra96-V2 board and I have made a design in Vivado where I just set the user leds to "0100". I have downloaded the constraints file from https://www.avnet.com/wps/portal/us/products/avnet-boards/avnet-board-families/ultra96-v2/ and following it I have added these lines to the io.xdc:

set_property PACKAGE_PIN AB4 [get_ports "leds[0]"];
set_property PACKAGE_PIN AA4 [get_ports "leds[1]"];
set_property PACKAGE_PIN Y5 [get_ports "leds[2]"];
set_property PACKAGE_PIN AA3 [get_ports "leds[3]"];

set_property IOSTANDARD LVCMOS18 [get_ports "leds[0]"];
set_property IOSTANDARD LVCMOS18 [get_ports "leds[1]"];
set_property IOSTANDARD LVCMOS18 [get_ports "leds[2]"];
set_property IOSTANDARD LVCMOS18 [get_ports "leds[3]"];

But I get an error:

[Place 30-494] The design is empty
Resolution: Check if opt_design has removed all the leaf cells of your design. Check whether you have instantiated and connected all of the top level ports.

And 16 warnings like this:

[Common 17-55] 'set_property' expects at least one object. [io.xdc":1]

 

Does anyone know how to solve this?

 

Thank you

0 Kudos
1 Reply
florentw
Moderator
Moderator
103 Views
Registered: ‎11-09-2015

Hi alonsosara44@gmail.com 

What is your design?

It seems that the design has been optimised so the implementation tool cannot find the port called "leds" 


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
0 Kudos