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Observer amitrasudan
Observer
9,680 Views
Registered: ‎03-12-2014

Unable to run implementation in OOC mode through Vivado GUI

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Hi,

 

While running implementation through batch mode or commands, my tcl script is doing the following:

 

################################################
###     SET DESIGN VARIABLES      ###
#################################################
set DesignName          "phif_top"
set PartName            "XC7V2000TFHG1761-2"
link_design -name ${DesignName} -part ${PartName} -mode out_of_context

 

 

 # optimize netlist
   opt_design
   #Place Design
   place_design
   # rebuffer high fanout nets
   phys_opt_design
   write_checkpoint -force $outputDir/post_place
   report_clock_utilization -file $outputDir/post_place_clock_util.rpt
   report_utilization -file $outputDir/post_place_util.rpt
  
   #  run router, report actual utilization and timing, write checkpoint design, run drc, write verilog and xdc out
   route_design
   write_checkpoint -force $outputDir/post_route
   report_timing_summary -file $outputDir/post_route_timing_summary.rpt
   report_timing -sort_by group -max_paths 100 -path_type summary -file $outputDir/post_route_timing.rpt
   report_utilization -file $outputDir/post_route_util.rpt
   report_power -file $outputDir/post_route_power.rpt
   report_drc -file $outputDir/post_imp_drc.rpt
   write_verilog -force $outputDir/bft_impl_netlist.v
   write_xdc -no_fixed_only -force $outputDir/bft_impl.xdc

################################################################

While running this script in batch mode, implementation completes successfully for the design.

 

But if I open a project in Vivado GUI, include the .edf and .xdc files as source files to the project and run a tcl script with only these below lines so that the design is OOC, then run implementation in GUI, then I am facing many errors :

 

################################################
###     SET DESIGN VARIABLES      ###
#################################################
set DesignName          "phif_top"
set PartName            "XC7V2000TFHG1761-2"
link_design -name ${DesignName} -part ${PartName} -mode out_of_context

 

The errors are for example:

[Place 30-415] IO Placement failed due to overutilization. This design contains 1336 I/O ports
 while the target  device: 7v2000t package: fhg1761, contains only 850 available user I/O. The target device has 850 usable I/O pins of which 0 are already occupied by user-locked I/Os.
 To rectify this issue:
 1. Ensure you are targeting the correct device and package.  Select a larger device or different package if necessary.
 2. Check the top-level ports of the design to ensure the correct number of ports are specified.
 3. Consider design changes to reduce the number of I/Os necessary.

Place [30-68] Instance IBUF_184 (IBUF) is not placed.

 

Please let me know where I am wrong, why I am unable to do implementation in OOC mode in Vivado GUI. Appreciate your help.

 

Thanks and regards,

Amitra

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1 Solution

Accepted Solutions
Xilinx Employee
Xilinx Employee
14,370 Views
Registered: ‎11-28-2007

Re: Unable to run implementation in OOC mode through Vivado GUI

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Hi Amitra,

 

The official flow is to add the netlist as Out-of-context DCP file to the project.

So run synthesis using -mode out_of_context, and then either setup the implementation runs in same project as synthesis, or add this DCP to a netlist project.

 

If you are using 3rd party synthesis you will first need to create an OOC checkpoint:

  • read_edif
  • link_design -mode out_of_context
  • write_checkpoint

 

 

Best regards,

Dries

--------------------------------------------------------------------------------------------------------------------
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4 Replies
Xilinx Employee
Xilinx Employee
9,676 Views
Registered: ‎09-20-2012

Re: Unable to run implementation in OOC mode through Vivado GUI

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Hi,

 

Did you create post synthesis project in vivado (for GUI mode)? If not try creating a post synthesis project as the top level is EDIF file.

 

In synthesis settings write -mode out_of _context in the more options field and run synthesis followed by Implementation.

 

Capture.PNG

There is no need of running link_design seperately from TCL when using GUI.

 

Check if the above works.

 

Regards,

Deepika.

Thanks,
Deepika.
--------------------------------------------------------------------------------------------
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Observer amitrasudan
Observer
9,666 Views
Registered: ‎03-12-2014

Re: Unable to run implementation in OOC mode through Vivado GUI

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Hi Deepika,

 

I have created the project as Post Synthesis project. The problem is as you showed in your snapshot, I am not seeing any settings for Synthesis where I can give the option "-mode out_of_context". Is it because synthesis is already performed and edf is already generated? I am not sure.

 

In my Project Settings I can see all the buttons on the left panel except "Synthesis" and "IP".

 

Thanks and regards,

Amitra

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Xilinx Employee
Xilinx Employee
14,371 Views
Registered: ‎11-28-2007

Re: Unable to run implementation in OOC mode through Vivado GUI

Jump to solution

Hi Amitra,

 

The official flow is to add the netlist as Out-of-context DCP file to the project.

So run synthesis using -mode out_of_context, and then either setup the implementation runs in same project as synthesis, or add this DCP to a netlist project.

 

If you are using 3rd party synthesis you will first need to create an OOC checkpoint:

  • read_edif
  • link_design -mode out_of_context
  • write_checkpoint

 

 

Best regards,

Dries

--------------------------------------------------------------------------------------------------------------------
Please mark the Answer as "Accept as solution" if the information provided is helpful.

Give Kudos to a post which you think is helpful and reply oriented by clicking the star next to the post.
Observer amitrasudan
Observer
9,643 Views
Registered: ‎03-12-2014

Re: Unable to run implementation in OOC mode through Vivado GUI

Jump to solution

Hi Dries,

 

Since I am using a third party generated edf netlist therefore, your solution worked. Previously, I was not reading the edf file and creating write checkpoints. After including them in the script along with link_design command and running implementation, I could complete the implementation without errors.

 

Thank you.

 

Regards,

Amitra

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