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Scholar embedded
Scholar
3,426 Views
Registered: ‎06-09-2011

Unplaced IODELAY_GROUP Problem

Hi,

I have used two IDELAY_CTRL for two modules in my design. One is being used for "Tri Mode Ethernet" core in my design. The other one is used inside my ADC_Module. When I tried to implement design I got below Error:

 

[Drc 23-20] Rule violation (PLIDC-1) IDELAYCTRL DRC Checks - IODELAY elements have been found to be associated with IODELAY_GROUP 'tri_mode_ethernet_mac_iodelay_grp', but there is no IDELAYCTRL associated with this IODELAY_GROUP.
[Drc 23-20] Rule violation (PLIDC-10) IDELAYCTRL DRC Checks - There are 27 IDELAY/ODELAY/IODELAY instances in the design which requires IDelayCtrl, but there is no IDelayCtrl instance
[Vivado_Tcl 4-23] Error(s) found during DRC. Placer not run.

 

Then I added below lines in my Ethernet module to assign a group to that IDELAY_CTRL used for "Tri Mode Ethernet".

 

attribute IODELAY_GROUP : STRING;
attribute IODELAY_GROUP of ETHIDLYAYCTRL_inst: label is "tri_mode_ethernet_mac_iodelay_grp";

begin
ETHIDLYAYCTRL_inst : IDELAYCTRL
port map (
RDY => open, -- 1-bit output: Ready output
REFCLK => iFastCLK, -- 1-bit input: Reference clock input
RST => sDLYCTRL_RST -- 1-bit input: Active high reset input

After this change in the code. I ran the Synthesis and then Implementation. I got below Errors regarding IDELAY2 elements inside my ADC_Module.

[Place 30-578] Found un-associated IO delay instances in the design. The list of IO delay instances without an associated IdelayCtrl is as follows:
ADC_Module_INST/ADC_Data_IDLY_GEN[0].IDLYAYE2_sADC_DAT_INST
ADC_Module_INST/ADC_Data_IDLY_GEN[15].IDLYAYE2_sADC_DAT_INST
ADC_Module_INST/ADC_Data_IDLY_GEN[2].IDLYAYE2_sADC_DAT_INST
ADC_Module_INST/ADC_Data_IDLY_GEN[1].IDLYAYE2_sADC_DAT_INST
ADC_Module_INST/IDLYAYE2_ADC_OR_INST
ADC_Module_INST/ADC_Data_IDLY_GEN[13].IDLYAYE2_sADC_DAT_INST
ADC_Module_INST/ADC_Data_IDLY_GEN[10].IDLYAYE2_sADC_DAT_INST
ADC_Module_INST/ADC_Data_IDLY_GEN[11].IDLYAYE2_sADC_DAT_INST
ADC_Module_INST/ADC_Data_IDLY_GEN[14].IDLYAYE2_sADC_DAT_INST
ADC_Module_INST/ADC_Data_IDLY_GEN[9].IDLYAYE2_sADC_DAT_INST
ADC_Module_INST/ADC_Data_IDLY_GEN[12].IDLYAYE2_sADC_DAT_INST
ADC_Module_INST/ADC_Data_IDLY_GEN[3].IDLYAYE2_sADC_DAT_INST
ADC_Module_INST/ADC_Data_IDLY_GEN[4].IDLYAYE2_sADC_DAT_INST
ADC_Module_INST/ADC_Data_IDLY_GEN[5].IDLYAYE2_sADC_DAT_INST
ADC_Module_INST/ADC_Data_IDLY_GEN[6].IDLYAYE2_sADC_DAT_INST
ADC_Module_INST/ADC_Data_IDLY_GEN[7].IDLYAYE2_sADC_DAT_INST
ADC_Module_INST/ADC_Data_IDLY_GEN[8].IDLYAYE2_sADC_DAT_INST

 

I have added this piece of code inside my ADC_Module:

attribute IODELAY_GROUP : STRING;
attribute IODELAY_GROUP of ADCIDLYAYCTRL_inst: label is "IDLYAYE2_sADC_DAT_INST";

begin

ADCIDLYAYCTRL_inst : IDELAYCTRL
.
.
.
.

However, placer can't detect to group this IDELAY_CTRL with those IODELAY2 elements inside my ADC_Module.

I am wondering if there is another way to specify such group or not?

I am using Vivado2014.4 and my FPGA is Kintex-7.

 

I appreciate any help.

Hossein

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3 Replies
Xilinx Employee
Xilinx Employee
3,391 Views
Registered: ‎04-16-2012

Re: Unplaced IODELAY_GROUP Problem

Hi @embedded

 

I suggest you to write IODELAY_GROUP xdc constraints in xdc file using below steps:

 

1. Open synthesized design and search for cells of type IDELAY/ODELAY/IDELAYCTRL.

2. Now write the below constraints to group all the IDELAY/IDELAYCTRL instance of IP and ADC to different groups using the constraint below in XDC.

 

set_property IODELAY_GROUP group_name [get_cells cell_name]

 

Thanks,

Vinay

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Scholar embedded
Scholar
3,376 Views
Registered: ‎06-09-2011

Re: Unplaced IODELAY_GROUP Problem

Hi @vuppala,

Thank you for your response. I have searched cells of type IDELAY_CTRL. It lists the IDELAY_CTRL cells in the search result list. However, I can't zoom in on the cell in the device view of opened synthesis file. Besides, I am wondering which name I should use as the name of that cell? Would you please help me in finding which name of the cells I should use?

I tried something like below line. But, it fails and doesn't work:

 

set_property IODELAY_GROUP IDELAYCTRL1 [get_cells IDELAYCTRL_X1Y1]

set_property IODELAY_GROUP IDELAYCTRL2 [get_cells IDELAYCTRL_X0Y3]

 

which "IDELAYCTRL1" & "IDELAYCTRL2" are the names I gave to two IDELAYCTRL primitives I used inside my ADC & Ethernet modules.

 

Thanks,

Hossein

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Xilinx Employee
Xilinx Employee
3,286 Views
Registered: ‎04-16-2012

Re: Unplaced IODELAY_GROUP Problem

Hi @embedded

 

In your case, xdc constraint looks like below:

 

set_property IODELAY_GROUP tri_mode_ethernet_mac_iodelay_grp [get_cells ETHIDLYAYCTRL]

set_property IODELAY_GROUP IDLYAYE2_SADC_DAT_INST [get_cells ADCIDLYAYCTRL]

 

Thanks,

Vinay

--------------------------------------------------------------------------------------------
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