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Registered: ‎02-08-2013

VHDL configuration late bind to CoreGen IP

Hi all,


using Planahead 14.6 on Windows x64.


Does anyone know if it's possible to implement late binding of CoreGen entities using a configuration?


Why? - say I have a component used in more than one project, and within that component is a filter. A configuration for one project might bind that filter component to a filter generated using CoreGen, and the second project might bind to a second filter generated by coregen. The generated IP filters might be used across projects, so are kept in a project neutral area and hence are generated in the wizard with different names - hence the late binding.





-- Instantiated in main hierarchy as "filter_block":


entity my_filter is


end entity;


architecture structure of my_filter is

        component a_filter


        end component;



        the_filter: a_filter

              port map(




       -- more logic


end architecture structure;



-- Project configuration


use work.all


configuration config1 of my_filter is

        for structure

                    for the_filter: a_filter

                             use entity work.my_coregen_CIC_filter1(my_coregen_CIC_filter1_a);

                    end for;

       end for;

end config1;




My Planahead project does see the filter core in my custom location (where the .xci file lives) and I can launch the wizard and change filter settings. The .ngc file has also been generated. 


Synthesis Completes.

Implementation fails with


            "Could not resolve non-primative black box cell 'a_filter' instatiated in module "top/filter_block"


It's looking for EDIF or NGC files with the name of the component, not the entity name the configuration says to 'plug into' the socket. I even added the path explicitly to where the ngc file of 'my_coregen_CIC_filter' is using the NGDBuild option '-sd' (although I feel the compiler should know about this as it is one of the IP core paths in the project).


I also notice the configuration file only has the 'Used In' options of 'Synthesis' and 'Simulation'.


If the generated NGC file has to have the same name as the component instance in my design, then what is the point of being able to late bind to different entities?



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2 Replies
Registered: ‎02-08-2013

Re: VHDL configuration late bind to CoreGen IP

So I found reference to this issue in this thread.


It basically says that external configurations are not supported. Can someone say if this is now supported in Vivado? 



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Community Manager
Community Manager
Registered: ‎06-14-2012

Re: VHDL configuration late bind to CoreGen IP

Is it possible to share the files? If yes, Please send to my email address

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