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felipe.oliveira
Observer
Observer
667 Views
Registered: ‎09-06-2019

[Vivado 12-1411] Cannot set LOC property of ports, loc is blocked

Hi,

I'm facing an issue reported as a critical warning with Vivado with no clue how to solve it. It is important to say that I'd implemented my design with Vivado 2019.1 and Vivado 2019.2 and the critical warning is reported in both cases. 

Talking specifically about the problem, we are developing a custom board with the xczu3cg device. This board have four RGMII interfaces implemented on PL with the TEMAC Xilinx IP (PG051). Before to manufacturing our prototypes, the pinout.xdc file was defined including all pins used on the project. On the design top level module, the lvds IO pins was defined according with the schematic requirements. Besides of that, it was added to the top level the block design with the four TEMAC implementing the RGMII interfaces. At this point, the Vivado wasn`t reporting any warning with the implementation and we start the manufacturing the prototypes. 

On the prototypes evaluation step, we start to add more functionality into the IO buffers. One of these functionalities is an IOBUF to a pin near to the rgmii_1_tx_clk signal (this pin was already defined as an inout, the only difference is the implementation of the primitive IOBUF). After that the Vivado change automatically the pin position chosen for the rgmii_1_txc_clk to an undesired position and report the message: [Vivado 12-1411] Cannot set LOC property of ports, loc is blocked.

I'm not sure if this warning is a design issue. I'd seen that the rgmii_tx_clk uses a cascade ODELAY and it is required to keep free the other DELAY near to it. But I'm not find anything about to use IOBUF near to the rgmii_tx_clk.

I hope that someone can help me with this issue.

Thanks in advance,

Felipe Oliveira

 

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7 Replies
felipe.oliveira
Observer
Observer
593 Views
Registered: ‎09-06-2019

Additional information about the problem:

1. It was also verified that this issue is reported when the IOBUF is declared as an input pin and is used to implement a combinational logic. 

2. The rgmii_1_txc_clk is constrained at k8 pin from the xczu3cg-sfvc784 device.

3. The other pin which appears to be useless is the H7.

 

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surajc
Xilinx Employee
Xilinx Employee
536 Views
Registered: ‎01-30-2019

HI @felipe.oliveira 

Could you please elaborate on the following statement of yours:- 
this pin was already defined as an inout, the only difference is the implementation of the primitive IOBUF

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felipe.oliveira
Observer
Observer
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Registered: ‎09-06-2019

Hi @surajc, thank you for your repply,

In this case, the issue is not reported by the Vivado when I only create the inout port and constraint it on .xdc file. The issue only happens if I effectively use the signal for some logic inside of the FPGA (using the IOBUF to manage the inout).

I'm testing some changes on the project and the same behavior is reported if the pin H7 from xczu3cg-sfvc784 device is an input and the pin K8 is constrained at rgmii_tx_clk from TEMAC. In this case, when I use the pin H7 to receive some signal and some logic is implemented with this signal, the pin K8 can't be constrained at rgmii_tx_clk from TEMAC - I believe that it is because of the cascade DELAY.

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surajc
Xilinx Employee
Xilinx Employee
493 Views
Registered: ‎01-30-2019

Hi @felipe.oliveira 

okay, in that case, Could you please create a simple test case showing this issue? so that we can debug further.

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felipe.oliveira
Observer
Observer
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Registered: ‎09-06-2019

Sure,

I'm attaching here the required files to regenerate a simple project reproducing the issue. Please let me know if any file is missing.

 

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felipe.oliveira
Observer
Observer
355 Views
Registered: ‎09-06-2019

hi @surajc,

Is there any update about my issue?

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surajc
Xilinx Employee
Xilinx Employee
292 Views
Registered: ‎01-30-2019

Hi @felipe.oliveira 

I checked your issue and this seems like a bug in Vivado 2019.2 as there is no such Critical Warning in Vivado 2020.2

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