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Adventurer
Adventurer
158 Views
Registered: ‎09-18-2018

Vivado 12-1411: XADC

Hi,

I get the following waring (that is problem for a lot of errors)

[Vivado 12-1411] Cannot set LOC property of ports, Could not legally place instance Vaux6_0_v_p_IBUF_inst at N15 (IOB_X1Y108) since it belongs to a shape containing instance design_1_i/xadc_wiz_0/U0/AXI_XADC_CORE_I/XADC_INST. The shape requires relative placement between Vaux6_0_v_p_IBUF_inst and design_1_i/xadc_wiz_0/U0/AXI_XADC_CORE_I/XADC_INST that can not be honoured because it would result in an invalid location for design_1_i/xadc_wiz_0/U0/AXI_XADC_CORE_I/XADC_INST. ["/home/Desktop/ISYS_SonicLightening/zybo_adc/zybo_adc.srcs/constrs_1/imports/Documents/masterlayout.xdc":104]

 

This is only happening in the case that I am using both RGB-Leds at the same time with the XADC on my zybo z7-20 board. If I use only one RGB-Led the are no problems!

 

Does someone know why, and how i can solve this problem?

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2 Replies
Xilinx Employee
Xilinx Employee
123 Views
Registered: ‎05-08-2012

Re: Vivado 12-1411: XADC

Hi @helplessguy.

 

From the 7-Series XADC Guide, it appears that no user LOC constraint is expected for the XDAC auxiliary ports. Can you try removing the constraint to N15 and any IOSTANDARD constraint? These should not fail the unconstrained IO check (UCIO-1) DRC, and would be an exception to general I/O behavior. 

https://www.xilinx.com/support/documentation/user_guides/ug480_7Series_XADC.pdf#page=29


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Xilinx Employee
Xilinx Employee
43 Views
Registered: ‎05-08-2012

Re: Vivado 12-1411: XADC

Hi @helplessguy.

Did the earlier response help, or did you find another solution? If so, marking this as a solution, and/or indicating how you resolved this could help other users.

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