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trevorbunker
Newbie
Newbie
12,208 Views
Registered: ‎10-09-2014

[Vivado 2014.3] Constraint 18-1079 Warnings

I just tried updating some AXI cores and re-building using Vivado 2014.3, but I am seeing dozens of these Constraint 18-1079 warnings. It seems to have a problem placing synchronizer flops in the same slice. The design is still functional, but it would be good to know if this is a tool issue or a design issue that wasn't reported in 2014.2. For example, here is one of the warnings:

 

WARNING: [Constraints 18-1079] Register u_axi_clock_converter_1/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_asreg_reg and u_axi_clock_converter_1/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_asreg_d1_reg are from the same synchronizer and have the ASYNC_REG property set, but could not be placed into the same slice due to constraints or mismatched control signals on the registers.

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graces
Moderator
Moderator
12,187 Views
Registered: ‎07-16-2008

Such warning is added in 2014.3 to inform user about the potential issue of synchronization.

 

If ASYNC_REG is applied, the placer will ensure the flip-flops on a synchronization chain are placed closely together in order to maximize MTBF. Registers with ASYNC_REG that are directly connected will be grouped and placed together into a single SLICE, assuming they have a compatible control set and the number of registers does not exceed the available resources of the SLICE.

This warning tells that the two registers have different control set signals (CE, SET/RESET) so that they cannot be packed into a single slice.

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frenschj
Visitor
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Registered: ‎06-12-2014

so that means - at least for my understanding - that something is implemented in a not-optimal way:

either the HDL is sub-optimally describing those control signals or synthesis is not correctly optimizing...

shouldn't that get fixed (by Xilinx!) ?

 

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markzak
Explorer
Explorer
11,726 Views
Registered: ‎12-01-2010

...so does this mean that we can ignore these warnings?

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jianwenchang
Contributor
Contributor
11,707 Views
Registered: ‎10-20-2014

 
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elod.gyorgy
Adventurer
Adventurer
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Registered: ‎01-23-2012

I am getting a lot of these warnings for several Xilinx IP. In most cases it can be ignored.

 

For example, the Test Pattern Generator instance has warnings between proc_sync1_reg[0] and data_sync_reg[0][0]. See the schematic below. Vivado is right, these two registers cannot be packed into the same slice, since they have different clocks.

The warning can be ignored because register proc_sync1_reg[0] is not part of the synchonizer. It pre-registers the signal probably so that it's glitch free and to keep the domain crossing in the tpg module. However, as far as I know, placing proc_sync1_reg[0] far away from the data_sync_reg FF chain won't affect the synchronizer's effectiveness. It shouldn't even have the ASYNC_REG set then.

 

async_reg_warning_tpg.png