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Adventurer
Adventurer
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Registered: ‎07-24-2018

Vivado 2016.1 Arty Z7-20 Implementation Error - A MMCM can only drive loads in the same clock region.

I've been trying to translate the image processing design targeting the Zybo board is here: http://web-pcm.cnfm.fr/wp-content/uploads/2017/04/Workbook-Digilent_ZYBO_Video_Workshop.pdf for the Arty-Z7-20.  My design validates and Synthesizes fine.  However, I get an error during Implementation that I can't seem to resolve.  

 

Block design:

pynq_hdmi_in_out_architecture.jpg

My constrains file is:

## This file is a general .xdc for the ARTY Z7-20 Rev.B
## To use it in a project:
## - uncomment the lines corresponding to used pins
## - rename the used ports (in each line, after get_ports) according to the top level signal names in the project


## Clock Signal
#set_property -dict { PACKAGE_PIN H16    IOSTANDARD LVCMOS33 } [get_ports { sys_clock }];

#####for MMCM error
#set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets design_1_i/rgb2dvi_0/U0/ClockGenInternal.ClockGenX/PixelClk]
#set_property CLOCK_DEDICATED_ROUTE BACKBONE [get_nets design_1_i/rgb2dvi_0/U0/ClockGenInternal.ClockGenX/PixelClk]
#####


## HDMI RX Signals
set_property -dict { PACKAGE_PIN P19   IOSTANDARD TMDS_33  } [get_ports { hdmi_in_clk_n }]; 
set_property -dict { PACKAGE_PIN N18   IOSTANDARD TMDS_33  } [get_ports { hdmi_in_clk_p }]; 
set_property -dict { PACKAGE_PIN W20   IOSTANDARD TMDS_33  } [get_ports { hdmi_in_data_n[0] }]; 
set_property -dict { PACKAGE_PIN V20   IOSTANDARD TMDS_33  } [get_ports { hdmi_in_data_p[0] }]; 
set_property -dict { PACKAGE_PIN U20   IOSTANDARD TMDS_33  } [get_ports { hdmi_in_data_n[1] }]; 
set_property -dict { PACKAGE_PIN T20   IOSTANDARD TMDS_33  } [get_ports { hdmi_in_data_p[1] }]; 
set_property -dict { PACKAGE_PIN P20   IOSTANDARD TMDS_33  } [get_ports { hdmi_in_data_n[2] }]; 
set_property -dict { PACKAGE_PIN N20   IOSTANDARD TMDS_33  } [get_ports { hdmi_in_data_p[2] }]; 
set_property -dict { PACKAGE_PIN U14   IOSTANDARD LVCMOS33 } [get_ports { hdmi_in_ddc_scl_io }]; 
set_property -dict { PACKAGE_PIN U15   IOSTANDARD LVCMOS33 } [get_ports { hdmi_in_ddc_sda_io }]; 

## HDMI TX Signals
set_property -dict { PACKAGE_PIN L17   IOSTANDARD TMDS_33  } [get_ports  hdmi_out_clk_n]; 
set_property -dict { PACKAGE_PIN L16   IOSTANDARD TMDS_33  } [get_ports  hdmi_out_clk_p ]; 
set_property -dict { PACKAGE_PIN K18   IOSTANDARD TMDS_33  } [get_ports { hdmi_out_data_n[0] }]; 
set_property -dict { PACKAGE_PIN K17   IOSTANDARD TMDS_33  } [get_ports { hdmi_out_data_p[0] }]; 
set_property -dict { PACKAGE_PIN J19   IOSTANDARD TMDS_33  } [get_ports { hdmi_out_data_n[1] }]; 
set_property -dict { PACKAGE_PIN K19   IOSTANDARD TMDS_33  } [get_ports { hdmi_out_data_p[1] }]; 
set_property -dict { PACKAGE_PIN H18   IOSTANDARD TMDS_33  } [get_ports { hdmi_out_data_n[2] }]; 
set_property -dict { PACKAGE_PIN J18   IOSTANDARD TMDS_33  } [get_ports { hdmi_out_data_p[2] }]; 
set_property -dict { PACKAGE_PIN R19   IOSTANDARD LVCMOS33 } [get_ports { hdmi_hpd }];


The error is related to the clock signal between the clocking wizard and the RGB-to-DVI block at the end.  The error message suggests to constraints that could resolve the issue:

 

[Place 30-154] Unroutable Placement! A MMCM can only drive loads in the same clock region. The following MMCM clock loads are placed too far from the MMCM to be routable. 
	design_1_i/rgb2dvi_0/U0/ClockGenInternal.ClockGenX/GenMMCM.DVI_ClkGenerator (MMCME2_ADV.CLKOUT0) is provisionally placed by clockplacer on MMCME2_ADV_X1Y0
	 design_1_i/rgb2dvi_0/U0/ClockSerializer/SerializerMaster (OSERDESE2.CLK) is locked to OLOGIC_X1Y128
	 design_1_i/rgb2dvi_0/U0/ClockSerializer/SerializerSlave (OSERDESE2.CLK) is locked to OLOGIC_X1Y127
	 design_1_i/rgb2dvi_0/U0/DataEncoders[0].DataSerializer/SerializerMaster (OSERDESE2.CLK) is locked to OLOGIC_X1Y126
	 design_1_i/rgb2dvi_0/U0/DataEncoders[0].DataSerializer/SerializerSlave (OSERDESE2.CLK) is locked to OLOGIC_X1Y125
	 design_1_i/rgb2dvi_0/U0/DataEncoders[1].DataSerializer/SerializerMaster (OSERDESE2.CLK) is locked to OLOGIC_X1Y130
	 design_1_i/rgb2dvi_0/U0/DataEncoders[1].DataSerializer/SerializerSlave (OSERDESE2.CLK) is locked to OLOGIC_X1Y129
	 design_1_i/rgb2dvi_0/U0/DataEncoders[2].DataSerializer/SerializerMaster (OSERDESE2.CLK) is locked to OLOGIC_X1Y122
	 design_1_i/rgb2dvi_0/U0/DataEncoders[2].DataSerializer/SerializerSlave (OSERDESE2.CLK) is locked to OLOGIC_X1Y121

	The above error could possibly be related to other connected instances. Following is a list of 
	all the related clock rules and their respective instances.

	Clock Rule: rule_mmcm_clklds
	Status: FAIL 
	Rule Description: An MMCM driving any number of IOBs must be placed within the same clock region
	 design_1_i/rgb2dvi_0/U0/ClockGenInternal.ClockGenX/GenMMCM.DVI_ClkGenerator (MMCME2_ADV.CLKOUT1) is provisionally placed by clockplacer on MMCME2_ADV_X1Y0
	 design_1_i/rgb2dvi_0/U0/ClockSerializer/SerializerMaster (OSERDESE2.CLKDIV) is locked to OLOGIC_X1Y128
	 design_1_i/rgb2dvi_0/U0/ClockSerializer/SerializerSlave (OSERDESE2.CLKDIV) is locked to OLOGIC_X1Y127
	 design_1_i/rgb2dvi_0/U0/DataEncoders[0].DataSerializer/SerializerMaster (OSERDESE2.CLKDIV) is locked to OLOGIC_X1Y126
	 design_1_i/rgb2dvi_0/U0/DataEncoders[0].DataSerializer/SerializerSlave (OSERDESE2.CLKDIV) is locked to OLOGIC_X1Y125
	 design_1_i/rgb2dvi_0/U0/DataEncoders[1].DataSerializer/SerializerMaster (OSERDESE2.CLKDIV) is locked to OLOGIC_X1Y130
	 design_1_i/rgb2dvi_0/U0/DataEncoders[1].DataSerializer/SerializerSlave (OSERDESE2.CLKDIV) is locked to OLOGIC_X1Y129
	 design_1_i/rgb2dvi_0/U0/DataEncoders[2].DataSerializer/SerializerMaster (OSERDESE2.CLKDIV) is locked to OLOGIC_X1Y122
	 design_1_i/rgb2dvi_0/U0/DataEncoders[2].DataSerializer/SerializerSlave (OSERDESE2.CLKDIV) is locked to OLOGIC_X1Y121
	ERROR: The above is also an illegal clock rule
	Workaround: < set_property CLOCK_DEDICATED_ROUTE BACKBONE [get_nets design_1_i/rgb2dvi_0/U0/ClockGenInternal.ClockGenX/PixelClk] >

	Clock Rule: rule_mmcm_mmcm
	Status: PASS 
	Rule Description: An MMCM driving an MMCM must be in the same CMT column, and they are adjacent to
	each other (vertically), if the  CLOCK_DEDICATED_ROUTE=BACKBONE constraint is NOT set
	 design_1_i/rgb2dvi_0/U0/ClockGenInternal.ClockGenX/GenMMCM.DVI_ClkGenerator (MMCME2_ADV.CLKFBOUT) is provisionally placed by clockplacer on MMCME2_ADV_X1Y0
	 and design_1_i/rgb2dvi_0/U0/ClockGenInternal.ClockGenX/GenMMCM.DVI_ClkGenerator (MMCME2_ADV.CLKFBIN) is provisionally placed by clockplacer on MMCME2_ADV_X1Y0


set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets design_1_i/rgb2dvi_0/U0/ClockGenInternal.ClockGenX/PixelClk]

-or-

set_property CLOCK_DEDICATED_ROUTE BACKBONE[get_nets design_1_i/rgb2dvi_0/U0/ClockGenInternal.ClockGenX/PixelClk]

 

When I try one it just tells me to try the other.  I'm really at a loss here - does anyone have any suggestions?

 

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Moderator
Moderator
548 Views
Registered: ‎01-16-2013

Re: Vivado 2016.1 Arty Z7-20 Implementation Error - A MMCM can only drive loads in the same clock region.

@dcc3

 

Looks to be a duplicate post. 

https://forums.xilinx.com/t5/Implementation/Vivado-2016-1-Implementation-Error/m-p/892608

 

Please avoid creating a duplicate post.

 

--Syed

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