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xromka
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Registered: ‎07-26-2017

Vivado 2017.2 reset FPGA if execute open_hw_target command

Hi.

Configuration: Vivado 2017.2, Windows7-64bit, Xilinx USB II JTAG programming cable.
FPGA board with the xcku085-flvb1760 chip. If this FPGA is programmed and I connect to FPGA thru JTAG programming cable, by executing the command in Flow Navigator:   "PROGRAM_AND_DEBUG -> Open_Target -> Auto_Connect "  this FPGA is resetting ( goes to unprogrammed state). This causes problems when debugging eg. PCIe.
Executing connecting command step by step I found the resetting FPGA is happening if execute  open_hw_target command.
Reset occurs only when connected - the subsequent work of JTAG has no problems.

 

Previously versions of Vivado (2016.4, 2017.1) on the same computer configuration and board doesn't reset FPGA if execute the open_hw_target command.

This is normal behavior for 2017.2 or it possible fix this?

 

Best regards, Roman.

 

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pratham
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Registered: ‎06-05-2013

@xromka Not heard on this as of now but could you please check if this could help you?

https://www.xilinx.com/support/answers/66954.html

-Pratham

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xromka
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Registered: ‎07-26-2017

Hi

I check two combinations of source for loading FPGA  (onboard paralel flash and JATG)  and  various combinations of power cycle and connection JTAG cable,  in any variants  behavior the same. I tested this solution "set_param labtools.auto_update_hardware 0" but no any effect.

In addition, when check a connection from Vivado 2017.1 I see that it uses hw_server 2017.2 so it seems to me that it's not about the hw_server settings.

Tcl console of Vivado 2017.1:
report_property [current_hw_server] Property Type Read-only Value CLASS string true hw_server HOST string true localhost ...
SID string true TCP:localhost:3121 SW_BUILD string true Thu Jun 15 18:38:54 2017 VERSION string true 2017.2

Best regards, Roman.

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pratham
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Registered: ‎06-05-2013

@xromka

 

This doesn’t happen during a later subsequent refresh_hw_device after programming?

 

Could you run below TCL command before opening hw_server?

set_param xicom.allow_cfgin_commands false

 

Could you please post the complete programming log and screenshots?

Run the hw_server with the below command line prior to running the program to a device and post the log here.

 

hw_server.bat –L<log filename> -l-

-Pratham

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xromka
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Registered: ‎07-26-2017

Hi

After connection and reloading FPGA (thru JTAG or from configuration memory) no any problem, command "refresh_hw_device" work correctly.

Runing "set_param xicom.allow_cfgin_commands false" before opening hw_server:

set_param xicom.allow_cfgin_commands false
0
open_hw
connect_hw_server
INFO: [Labtools 27-2285] Connecting to hw_server url TCP:localhost:3121
open_hw_target
INFO: [Labtoolstcl 44-466] Opening hw_target localhost:3121/xilinx_tcf/Xilinx/000013ca270301
current_hw_device [get_hw_devices xcku085_1]
refresh_hw_device [lindex [get_hw_devices xcku085_1] 0]
INFO: [Labtools 27-1434] Device xcku085 (JTAG device index = 1) is programmed with a design that has no supported debug core(s) in it.
WARNING: [Labtools 27-3361] The debug hub core was not detected.
...

FPGA reset in connection time so no found debug core,  but after then, FPGA reloading automatically(!?) from the configuration memory.

...
2. Goto device properties and associate the correct probes file(s) with the programming file already programmed in the device.
create_hw_cfgmem -hw_device [lindex [get_hw_devices] 1] -mem_dev [lindex [get_cfgmem_parts {s29gl01gs-bpi-x16}] 0]
refresh_hw_device [lindex [get_hw_devices xcku085_1] 0]
INFO: [Labtools 27-2302] Device xcku085 (JTAG device index = 1) is programmed with a design that has 4 ILA core(s).
INFO: [Labtools 27-2302] Device xcku085 (JTAG device index = 1) is programmed with a design that has 1 JTAG AXI core(s).

Below you can find two log files that were written when you started hw_server v2017.2.

Initial state: FPGA is loaded from the onboard configuration memory.
Hw_srv_2017_1.txt - The log when connecting Vivado 2017.1. FPGA is not reset after connection.
Hw_srv_2017_2.txt - The log when connecting Vivado 2017.2. FPGA reset after connection.

Best regards, Roman.

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xromka
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Registered: ‎07-26-2017

 Hi,

 

@pratham No any new ideas about this problem?

 

Best regards, Roman.

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