cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
vanshika_chawla
Observer
Observer
1,365 Views
Registered: ‎11-07-2018

Vivado 2018.2 Implementation

Jump to solution

Hello,

 

I am currently using Vivado 2018.2 for Zynq7045. This project is being migrated from Virtex6 based implementation using ISE 14.7. 

Majority of our changes are to upgrade older LogicCore IFFT IP(7.1) to 9.1 and similar for dividers and block memories.

The Netlist generated after Implementation has very few nets and all blocks interfaced directly to IFFT module including the IFFT module itself are getting optimized out. The Synthesized Netlist has all the nets required for the project as well as the IFFT and related modules. 

I am unable to understand the reason why over 3000 nets and the IFFT and related modules are being optimized.

 

 Could you please help me with this problem? I can provide more relevant details as long as they are generic and do not disclose anything major about the design.

 

-Vanshika

0 Kudos
Reply
1 Solution

Accepted Solutions
graces
Moderator
Moderator
1,349 Views
Registered: ‎07-16-2008

You may try to enable -debug_log option in opt_design to get more information about suspicious optimizations.

A few possible causes for the trimming:

  1. Could be due to a clock or control signal that became constant.
  2. A reduced signal entering a cone of logic that pushes forward and optimizes away lots of logic in its path.
  3. A loadless driver that is swept backwards, also sweeping lots of upstream logic.
-------------------------------------------------------------------------
Don't forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------

View solution in original post

4 Replies
graces
Moderator
Moderator
1,350 Views
Registered: ‎07-16-2008

You may try to enable -debug_log option in opt_design to get more information about suspicious optimizations.

A few possible causes for the trimming:

  1. Could be due to a clock or control signal that became constant.
  2. A reduced signal entering a cone of logic that pushes forward and optimizes away lots of logic in its path.
  3. A loadless driver that is swept backwards, also sweeping lots of upstream logic.
-------------------------------------------------------------------------
Don't forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------

View solution in original post

syedz
Moderator
Moderator
1,327 Views
Registered: ‎01-16-2013

@vanshika_chawla

 

Open the synthesized design and run opt_design -verbose -debug_log which will give additional details.

check the following answer record: 

https://www.xilinx.com/support/answers/58616.html

 

For details of "Logic Optimization" check this link: 

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2018_2/ug904-vivado-implementation.pdf#page=51

 

--Syed

 

---------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.

Did you check our new quick reference timing closure guide (UG1292)?
---------------------------------------------------------------------------------------------
Tags (1)
vanshika_chawla
Observer
Observer
1,289 Views
Registered: ‎11-07-2018

I added dont_touch to the RTL files. The nets are not being removed now. But I would still like to know the actual reason the nets are being removed. 

0 Kudos
Reply
vanshika_chawla
Observer
Observer
1,286 Views
Registered: ‎11-07-2018

I was able to enable verbose for opt_design. The log files showed that lots of nets were being removed. 

I am still unsure about the reason its being optimized.

 

-Vanshika

0 Kudos
Reply