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541 Views
Registered: ‎11-07-2018

Vivado 2018.2 Implementation

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Hello,

 

I am currently using Vivado 2018.2 for Zynq7045. This project is being migrated from Virtex6 based implementation using ISE 14.7. 

Majority of our changes are to upgrade older LogicCore IFFT IP(7.1) to 9.1 and similar for dividers and block memories.

The Netlist generated after Implementation has very few nets and all blocks interfaced directly to IFFT module including the IFFT module itself are getting optimized out. The Synthesized Netlist has all the nets required for the project as well as the IFFT and related modules. 

I am unable to understand the reason why over 3000 nets and the IFFT and related modules are being optimized.

 

 Could you please help me with this problem? I can provide more relevant details as long as they are generic and do not disclose anything major about the design.

 

-Vanshika

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Xilinx Employee
Xilinx Employee
525 Views
Registered: ‎07-16-2008

回复: Vivado 2018.2 Implementation

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You may try to enable -debug_log option in opt_design to get more information about suspicious optimizations.

A few possible causes for the trimming:

  1. Could be due to a clock or control signal that became constant.
  2. A reduced signal entering a cone of logic that pushes forward and optimizes away lots of logic in its path.
  3. A loadless driver that is swept backwards, also sweeping lots of upstream logic.
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4 Replies
Xilinx Employee
Xilinx Employee
526 Views
Registered: ‎07-16-2008

回复: Vivado 2018.2 Implementation

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You may try to enable -debug_log option in opt_design to get more information about suspicious optimizations.

A few possible causes for the trimming:

  1. Could be due to a clock or control signal that became constant.
  2. A reduced signal entering a cone of logic that pushes forward and optimizes away lots of logic in its path.
  3. A loadless driver that is swept backwards, also sweeping lots of upstream logic.
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Don't forget to reply, kudo, and accept as solution.
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Moderator
Moderator
503 Views
Registered: ‎01-16-2013

Re: Vivado 2018.2 Implementation

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@vanshika_chawla

 

Open the synthesized design and run opt_design -verbose -debug_log which will give additional details.

check the following answer record: 

https://www.xilinx.com/support/answers/58616.html

 

For details of "Logic Optimization" check this link: 

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2018_2/ug904-vivado-implementation.pdf#page=51

 

--Syed

 

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465 Views
Registered: ‎11-07-2018

Re: Vivado 2018.2 Implementation

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I added dont_touch to the RTL files. The nets are not being removed now. But I would still like to know the actual reason the nets are being removed. 

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462 Views
Registered: ‎11-07-2018

回复: Vivado 2018.2 Implementation

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I was able to enable verbose for opt_design. The log files showed that lots of nets were being removed. 

I am still unsure about the reason its being optimized.

 

-Vanshika

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