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Explorer
Explorer
767 Views
Registered: ‎11-29-2015

Vivado 2018.3 route_design ERROR due to seg fault during implementation

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What do you need to be able to find out specifically why route_design failed?

ubuntu 18.04 LTS

Vivado 2018.3

Flow_Quick succeeds. 

Implementation_Defaults fails:

Time (s): cpu = 00:00:39 ; elapsed = 00:00:20 . Memory (MB): peak = 2900.430 ; gain = 92.535 ; free physical = 287 ; free virtual = 42598

Phase 4 Rip-up And Reroute

Phase 4.1 Global Iteration 0
Abnormal program termination (11)
Please check '/home/david/Code/Stereo_Correspondence/FPGA_Sentry.runs/impl_3/hs_err_pid5687.log' for details

Performance_ExploreWithRemap fails as well:

Reason 1:
Time (s): cpu = 00:00:12 ; elapsed = 00:00:06 . Memory (MB): peak = 2446.352 ; gain = 372.398 ; free physical = 342 ; free virtual = 43124
/tools/Xilinx/Vivado/2018.3/bin/loader: line 213:  9885 Segmentation fault      (core dumped) "$RDI_PROG" "$@"

Reason 2:

Abnormal program termination (8)
Please check '/home/david/Code/Stereo_Correspondence/FPGA_Sentry.runs/impl_6/hs_err_pid29144.log' for details

 

Logs are attached

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Explorer
Explorer
589 Views
Registered: ‎11-29-2015

Re: Vivado 2018.3 route_design ERROR due to seg fault during implementation

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@marcb

The "set_param general.maxThreads 1" option may have worked but then I don't get to use the 8 cores on my CPU. What good is that?

 

Apparently "There is a bug in Vivado which causes it to double free a pthread mutex. Using a glibc configured with --disable-lock-elision prevents this from being recognized on CPUs with the TSX extension."

https://www.reddit.com/r/FPGA/comments/4olc29/is_anyone_running_vivado_2016x_on_a_recent_ubuntu/

I tested the same project on Ubuntu 18.04 LTS and CentOS 7.6 and had the same issues shown in my previous replies. Basically, this is some old bug that has to do with glibc that Xilinx never fixed. Thanks Xilinx. It seems like it might only affect overclockable intel processors (with K in the model number) but I'm not sure. It may just be a coincidence. One solution is to replace glibc with some other version, as mentioned in the link above. Another solution is to replace some *.o file in the vivado installation. Another solution is to replace linux with windows 10 :-). I like that I got to waste a few days of my life because Xilinx/Vivado QA doesn't bother to test thoroughly enough. That was fun.

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6 Replies
Moderator
Moderator
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Registered: ‎01-16-2013

Re: Vivado 2018.3 route_design ERROR due to seg fault during implementation

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@david12341234

 

Flow_Quick is not timing driven strategy. I believe the issue is caused by timing constraints in the design. 

Are there any complex timing constraints which can be simplified? Try to comment and uncomment the constraints to narrow down which set of constraints is causing the crash. 

 

The expectation from the tool is to never crash but instead, give a proper error message to users. Can you share the vivado archive project to debug it at our end? If yes, I can send you private message which has link to upload project.

I can forward it to Factory to get it fixed in Vivado and also get you a workaround to continue with the design. 

 

--Syed

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Did you check our new quick reference timing closure guide (UG1292)?
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Explorer
Explorer
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Registered: ‎11-29-2015

Re: Vivado 2018.3 route_design ERROR due to seg fault during implementation

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@syedz

I can't share the code. The bottom line is that regardless of timing constraints, the process isn't supposed to crash. It should just produce the best results that it can. What is the actual cause of the crash? It ran out of memory?

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Xilinx Employee
Xilinx Employee
686 Views
Registered: ‎05-08-2012

Re: Vivado 2018.3 route_design ERROR due to seg fault during implementation

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Hi @david12341234.

I do not see this as being a previously reported issue, based on a search from the crash log information. If a reproducible design is not available, I would suggest finding the constraint(s) related to the failure. One way would be to commenting out constraints to find which one is related to the problem. Once found, there might be an equivelent alternative for the constraint, or possibly a DONT_TOUCH could be used on the logic related to this.


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Explorer
Explorer
672 Views
Registered: ‎11-29-2015

Re: Vivado 2018.3 route_design ERROR due to seg fault during implementation

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@marcb

 

I have keep_hierarchy set to true on all my entities but it has gone through the full synthesis-implementation-bitstream process before. I'm just making small changes. I don't have any timing constraints set that were not already set on doezens of previously successful runs. The main point here is that the process should not crash. It should finish and possibly produce a less than desirable result. If it does crash, the log should tell you waht you need to know to advise on a potential solution.

 

edit:

I commented out keep_hierarchy everywhere in the design. I'm not using dont_touch. Still crashes. Log attached.

Time (s): cpu = 00:00:59 ; elapsed = 00:00:30 . Memory (MB): peak = 2802.910 ; gain = 0.000 ; free physical = 8986 ; free virtual = 44555

Phase 3.5 Fast Optimization
Abnormal program termination (8)
Please check '/home/david/Code/Stereo_Correspondence/FPGA_Sentry.runs/impl_3/hs_err_pid13945.log' for details

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Xilinx Employee
Xilinx Employee
645 Views
Registered: ‎05-08-2012

Re: Vivado 2018.3 route_design ERROR due to seg fault during implementation

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Hi @david12341234.

I agree that a crash should not happen. I would like to report the issue to have it fixed, but a reproducible design is required for this. Do any of the example Vivado designs reproduce this issue that could be sent?

This would be more difficult to narrow down a suggestion, since the issue is seen in both place_design and route_design, and has at least 3 different crash logs. I do see threading information from the crash logs, so the below parameter could be tried. Other than this, I would suggest submitting a non-proprietary example design that reproduces.

set_param general.maxThreads 1


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Explorer
Explorer
590 Views
Registered: ‎11-29-2015

Re: Vivado 2018.3 route_design ERROR due to seg fault during implementation

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@marcb

The "set_param general.maxThreads 1" option may have worked but then I don't get to use the 8 cores on my CPU. What good is that?

 

Apparently "There is a bug in Vivado which causes it to double free a pthread mutex. Using a glibc configured with --disable-lock-elision prevents this from being recognized on CPUs with the TSX extension."

https://www.reddit.com/r/FPGA/comments/4olc29/is_anyone_running_vivado_2016x_on_a_recent_ubuntu/

I tested the same project on Ubuntu 18.04 LTS and CentOS 7.6 and had the same issues shown in my previous replies. Basically, this is some old bug that has to do with glibc that Xilinx never fixed. Thanks Xilinx. It seems like it might only affect overclockable intel processors (with K in the model number) but I'm not sure. It may just be a coincidence. One solution is to replace glibc with some other version, as mentioned in the link above. Another solution is to replace some *.o file in the vivado installation. Another solution is to replace linux with windows 10 :-). I like that I got to waste a few days of my life because Xilinx/Vivado QA doesn't bother to test thoroughly enough. That was fun.

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