01-10-2019 05:45 AM
When running write _bitstream from bot the tcl console and the GUI (on a Centos 7 machine).
The process starts but never ends.
This is all that gets logged.
Command: write_bitstream -force fae_test_chip2z.bit -verbose
Attempting to get a license for feature 'Implementation' and/or device 'xc7z020'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020'
Running DRC as a precondition to command write_bitstream
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/xilinx/Vivado/2018.3/data/ip'.
01-10-2019 06:26 AM
Make sure you are using supported centos version - CentOS 7.2, 7.3, 7.4, and 7.5 (64-bit) for Vivado 2018.3.
And provide vivado.log from your project directory. Also provide any crash log present like hs_pid_xxx.
01-10-2019 07:21 AM
01-10-2019 08:03 AM
Provide runme.log from : /projects/tests/vivado_bitstream/project_1/project_1.runs/impl_1/runme.log
Try to run bitstream from another machine, if possible with supported Centos OS version.
01-10-2019 12:07 PM
I managed to get an old VM running Centos 7.4 going with the tools.
I get the same behaviour with write_bitstream.
01-10-2019 07:55 PM
Can you share your archived project to regenerate this issue at my end?
I have sent you an ezmove ftp package through which you can provide your archived project.
01-11-2019 02:16 AM - edited 01-11-2019 02:17 AM
Check if the machine has enough memory. Is this specific to one project? Can you try a xilinx example design and check?
Also run report_methodology and report_drc and validate the warnings and critical warning.
In the vivado.log, I see the following warning:
WARNING: [Board 49-26] cannot add Board Part digilentinc.com:genesys2:part0:1.1
01-11-2019 03:05 AM
The Machine has 32GB Ram. (Nothing else is running on it)
It is not specific to one project. The archive I sent is just a little test case.
I saw the digilent warnings as well. I think they come from adding the digilent board support files to the Vivado config.
I did try and load up the ZyboZ7-20 DMA Reference project and got the same result.
There are no issues reported on the test project for report_methodology and report_drc and validate the warnings and critical warning.
01-11-2019 03:09 AM
Can you try with xilinx device or board? If it doesn't work then try reinstalling the tool.
01-14-2019 03:35 AM
So in Summary at this point I have tried
Centos 7.6 and 7.4
A full software re-install.
Targeted both the ZyboZ7 board and the device directly.
The test design is simply an AXIS FIFO with the generated wrapper.
The Machine has 32GB RAM.
DRC looks OK.
No critical warnings.
Tried both in the GUI and from the tcl shell.
In all cases the process just runs forever without using much in the way of CPU cycles.
01-14-2019 05:51 AM
From the provided archived project i am not able to reproduce the bitstream hang issue. And i am facing DRC error while generating bitstream. (As shown below.)
Hence, please provide the correct project to reproduce the issue.
01-14-2019 07:03 AM
Sorry about that confusion. My original design had no critical warnings.
There were messages about unconstrained pins on the quick test design but I only see them if I don't try and run bitgen.
I have them constrained now, but it still doesn't get through write_bitstream.
If I just run implementation this completes and I get DRC results. No critical warnings.
Select Generate Bitstream synthesis goes out of date bitstream runs forever.
Reset the step. Select run Bitstream again. The process starts from the beginning (The DRC Violations stays at "Run implementation to see DRC results" and write_bitstream runs forever. I can upload a new archive.
I can upload the
01-14-2019 07:43 AM
I have sometimes run into weird situations where I could get out only by starting a fresh project and dropping in the source files. Have you been doing major changes in your project? Vivado seems to be sensitive to that.
01-14-2019 07:50 AM
My build flow does that actually for every build. I am using HDLMAKE to run the builds. This grates a new project every time you run make.
My simple Test case (just using Vivado) is nothing more than opening Vivado and instantating an AXIS FIFO. Making all ports external and building it. (I did have to fiddle around to get the I/Os all constrained).
01-14-2019 12:54 PM
A couple of attempts with the updated archive did not reproduce using CentOS 7.4 and 2018.3. Do you see the problem without a Make file?
Don’t forget to reply, kudo, and accept as solution.
01-14-2019 01:56 PM
Thanks for trying this Marc
I am not using a make file for the small test case that I uploaded, Just running it directly in Vivado.
I just tried it again here, Both machines do the same thing. CPU usage goes to near 0 and write_bitstream runs forever.
I take you got a bitstream out?
01-16-2019 06:05 AM
Looking more like either a Vivado install script issue or a system package issue. It's frustrating that it just spins with no indication of what might be wrong.
01-17-2019 05:44 AM
I tried running write_bitstream as root. It still just ran forever. So this should not be a file permissions issue.
Also tried it on a fresh Centos 7.5 VM and got the same result.