09-20-2019 04:57 PM
I try to realize some TDC. And as first target I try to implement wave union based on CARRY4 primitives.
I've successfuly simulated it, but after implementation is generated - it doesn't work.
Then I've found, that on two CARRY instances the CI and CYINIT inputs are mixed up.
After synthesis it is everything ok, but after implementation not
This are tho fragments of schematic after sinthesis.
And now are same fragments after implementation:
Independent from implementation strategy I get always wrong routing for 1 and 16 CARRY4 elements.
I've found AR# 62073 and tryed to put
set_param synth.elaboration.rodinMoreOptions "rt::set_parameter constPropCarry false"
to some tcl file and configure it as tcl.pre script. Maybe I made it wrong?
But I've not found a solution how to force vivado do not to replace CI and CYINIT.
In attachment is the ring oscillator based on CARRY4 and the test fixture for simulation.
Can sombody help me?
09-21-2019 07:09 AM
I don't know if it is a good solution, but after I've defined the wite to the CI pin as DONT_TOUCH = "yes", there was no fron connection more.
(* DONT_TOUCH = "yes" *)(* KEEP = "TRUE" *) wire [(C_S_DELAY_LINE_LENGTH * 4) - 1 : 0] s;
09-30-2019 04:13 AM - edited 09-30-2019 04:15 AM
Hi @dgo42 ,
The solution of applying DONT_TOUCH attribute is very correct and you can move ahead with that WorkAround.
DONT_TOUCH will avoid any optimization or changes to be applied on the specific net or signal or instance.