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Visitor pyzahl
Visitor
815 Views
Registered: ‎02-26-2018

Vivado 2019.1 IOBUF changes vs. 2018.7 or upgrade problems?

Hello!

I have a still unresolved problem using IOBUF -- it stopped working after upgrading a previously working project from Vivado18.7 to 19.1. I do not find any related error messages or a like. The design works as far as I can tell, except I am not getting any IO outputs (and potentiall input) on my digital interface any more.

Any hints what could have went wrong or what to check for?

I use IO defined like this in the xdc file:

set_property IOSTANDARD LVCMOS33 [get_ports {exp_p_io[*]}]
set_property IOSTANDARD LVCMOS33 [get_ports {exp_n_io[*]}]
set_property SLEW FAST [get_ports {exp_p_io[*]}]
set_property SLEW FAST [get_ports {exp_n_io[*]}]
set_property DRIVE 8 [get_ports {exp_p_io[*]}]
set_property DRIVE 8 [get_ports {exp_n_io[*]}]

set_property PACKAGE_PIN G17 [get_ports {exp_p_io[0]}]
set_property PACKAGE_PIN G18 [get_ports {exp_n_io[0]}]
set_property PACKAGE_PIN H16 [get_ports {exp_p_io[1]}]
... and the remaining pins a like.

 

via this module:

 

module McBSP_io_connect #(
)
(
// inout logic [ 8-1:0] exp_p_io,
inout [8-1:0] exp_p_io,
inout [8-1:0] exp_n_io,
input McBSP_clkr, // CLKR: clock return
input McBSP_tx, // TX: data transmit
input McBSP_fsx, // optional, debug: data frame start FSX
input McBSP_frm, // optional, debug: data frame
output McBSP_clk, // McBSP clock
output McBSP_fs, // McBSP FS (frame start)
output McBSP_rx, // McBSP RX (data receive)
output McBSP_nrx, // optional: Nth/other RedPitaya slaves data TX forwarded on scheme TDB
output [8-1:0] RP_exp_in
);

wire [4-1:0] dummy;

IOBUF clk_iobuf (.O(McBSP_clk), .IO(exp_p_io[0:0]), .I(0), .T(1) );
IOBUF fs_iobuf (.O(McBSP_fs), .IO(exp_p_io[1:1]), .I(0), .T(1) );
IOBUF rx_iobuf (.O(McBSP_rx), .IO(exp_p_io[2:2]), .I(0), .T(1) );
IOBUF tx_iobuf (.O(dummy[0]), .IO(exp_p_io[3:3]), .I(McBSP_tx), .T(0) );
IOBUF fsx_iobuf (.O(dummy[1]), .IO(exp_p_io[4:4]), .I(McBSP_fsx), .T(0) );
IOBUF frm_iobuf (.O(dummy[2]), .IO(exp_p_io[5:5]), .I(McBSP_frm), .T(0) );
IOBUF clkr_iobuf(.O(dummy[3]), .IO(exp_p_io[6:6]), .I(McBSP_clkr),.T(0) );
IOBUF nrx_iobuf (.O(McBSP_nrx), .IO(exp_p_io[7:7]), .I(0), .T(1) );

IOBUF exp_in_iobuf[8-1:0] (.O(RP_exp_in), .IO(exp_n_io), .I(8'b00000000), .T(8'b11111111) );

endmodule

 

best

-Percy

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14 Replies
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Scholar richardhead
Scholar
797 Views
Registered: ‎08-01-2012

Re: Vivado 2019.1 IOBUF changes vs. 2018.7 or upgrade problems?

Vivado 2018.7 doesnt exist, the final version was 2018.3

Teacher drjohnsmith
Teacher
792 Views
Registered: ‎07-09-2009

Re: Vivado 2019.1 IOBUF changes vs. 2018.7 or upgrade problems?

Typical problems come on upgrading when u have locked ip. If u have any, try updating the ip in your design. Its a separate process.
<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
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Visitor pyzahl
Visitor
784 Views
Registered: ‎02-26-2018

Re: Vivado 2019.1 IOBUF changes vs. 2018.7 or upgrade problems?

Thanks for the quick hint.

I did checked all IP's, and all are set to auto update and up-to-date. (if that is what you mean with (not) locked).

I noticed this, but no idea what that means if anyrthing for me:

WARNING: [Common 17-576] 'use_project_ipc' is deprecated.

 

---

This is the report of the module in question or using IOBIF

Report Cell Usage:
+------+------+------+
| |Cell |Count |
+------+------+------+
|1 |IOBUF | 16|
+------+------+------+

Report Instance Areas:
+------+---------+-----------------+------+
| |Instance |Module |Cells |
+------+---------+-----------------+------+
|1 |top | | 16|
|2 | inst |McBSP_io_connect | 16|
+------+---------+-----------------+------+
---------------------------------------------------------------------------------
Finished Writing Synthesis Report : Time (s): cpu = 00:00:12 ; elapsed = 00:00:16 . Memory (MB): peak = 1885.773 ; gain = 359.121 ; free physical = 6068 ; free virtual = 13638
---------------------------------------------------------------------------------
Synthesis finished with 0 errors, 0 critical warnings and 0 warnings.
Synthesis Optimization Runtime : Time (s): cpu = 00:00:11 ; elapsed = 00:00:14 . Memory (MB): peak = 1885.773 ; gain = 217.371 ; free physical = 6124 ; free virtual = 13694
Synthesis Optimization Complete : Time (s): cpu = 00:00:13 ; elapsed = 00:00:16 . Memory (MB): peak = 1885.773 ; gain = 359.121 ; free physical = 6124 ; free virtual = 13694
INFO: [Project 1-571] Translating synthesized netlist
INFO: [Netlist 29-17] Analyzing 16 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-570] Preparing netlist for logic optimization
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1885.773 ; gain = 0.000 ; free physical = 6035 ; free virtual = 13638
INFO: [Project 1-111] Unisim Transformation Summary:
A total of 12 instances were transformed.
IOBUF => IOBUF (IBUF, OBUFT): 12 instances

INFO: [Common 17-83] Releasing license: Synthesis
22 Infos, 2 Warnings, 0 Critical Warnings and 0 Errors encountered.
synth_design completed successfully
synth_design: Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1885.773 ; gain = 556.555 ; free physical = 5971 ; free virtual = 13728
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1885.773 ; gain = 0.000 ; free physical = 5969 ; free virtual = 13728
WARNING: [Constraints 18-5210] No constraints selected for write.
Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened.
INFO: [Common 17-1381] The checkpoint '/home/pzahl/SVN/RedPitaya/RedPitayaPACPLL4mdc-McBSP-201909/RedPitayaPACPLL4mdc-McBSP-201909.runs/system_McBSP_io_connect_0_0_synth_1/system_McBSP_io_connect_0_0.dcp' has been generated.
WARNING: [Common 17-576] 'use_project_ipc' is deprecated. This option is deprecated and no longer used.
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1885.773 ; gain = 0.000 ; free physical = 6154 ; free virtual = 13727
WARNING: [Constraints 18-5210] No constraints selected for write.
Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened.
INFO: [Common 17-1381] The checkpoint '/home/pzahl/SVN/RedPitaya/RedPitayaPACPLL4mdc-McBSP-201909/RedPitayaPACPLL4mdc-McBSP-201909.runs/system_McBSP_io_connect_0_0_synth_1/system_McBSP_io_connect_0_0.dcp' has been generated.
INFO: [runtcl-4] Executing : report_utilization -file system_McBSP_io_connect_0_0_utilization_synth.rpt -pb system_McBSP_io_connect_0_0_utilization_synth.pb
INFO: [Common 17-206] Exiting Vivado at Sat Sep 28 15:32:44 2019...

 

 

 

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Teacher drjohnsmith
Teacher
770 Views
Registered: ‎07-09-2009

Re: Vivado 2019.1 IOBUF changes vs. 2018.7 or upgrade problems?

Sorry, I dont have any other idea,
I Know "use_project_ipc" is a tcl command, but not much more.
<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
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Visitor pyzahl
Visitor
678 Views
Registered: ‎02-26-2018

Re: Vivado 2019.1 IOBUF changes vs. 2018.7 or upgrade problems?

Sorry, I still have the same unresloved issue pending.

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Moderator
Moderator
647 Views
Registered: ‎03-16-2017

Re: Vivado 2019.1 IOBUF changes vs. 2018.7 or upgrade problems?

Hi @pyzahl

>> The design works as far as I can tell, except I am not getting any IO outputs (and potential input) on my digital interface anymore.

So I believe, you are facing the wrong functionality on the hardware. Correct me if my understanding is wrong. 

 

Can you do check with behavioral simulation and post-synthesis functional simulation with Vivado 2019.1 and see that you are getting the desired functionality or not? It will show where the discrepancy got started.

 

 

Regards,
hemangd

Don't forget to give kudos and mark it as accepted solution if your issue gets resolved.
Visitor pyzahl
Visitor
634 Views
Registered: ‎02-26-2018

Re: Vivado 2019.1 IOBUF changes vs. 2018.7 or upgrade problems?

This is a great idea, but I am not familiar with creating a simulation for applying actual signals to a external pins? So far I only have simulations for more complex modules in a stand alone manner to check for functionality.

So far I used a actual logic tester to check on signals on physical pins. And I know the signal is getting there. Also the 2018.7  FPGA bitcode file works if I load it. As created before the upgrade.

Or do you mean simulating the higher level modules "feeding or reading/using" this "McBSP_io_connect" module for functionality?

sorry asking

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Visitor pyzahl
Visitor
614 Views
Registered: ‎02-26-2018

Re: Vivado 2019.1 IOBUF changes vs. 2018.7 or upgrade problems?

Hi!

I managed to run my simution and also run it as "post-synthesis functional simulation", as of the parts I simulated I can not find a problem and both are the same and look OK. I will test the latest bit file again in the actual hardware, but did not changed anything.

The inout pins connected via exp_p_io[] are workign here:

Screenshot from 2019-10-19 20-36-35.png

thanks. Update on actual hardware results follow.

-Percy

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Visitor pyzahl
Visitor
605 Views
Registered: ‎02-26-2018

Re: Vivado 2019.1 IOBUF changes vs. 2018.7 or upgrade problems?

Still no digital IO function with the new build :(

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Teacher drjohnsmith
Teacher
560 Views
Registered: ‎07-09-2009

Re: Vivado 2019.1 IOBUF changes vs. 2018.7 or upgrade problems?

if you can post the code as an attachment, I can have a look, If you need it do more than one post
<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
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Visitor pyzahl
Visitor
537 Views
Registered: ‎02-26-2018

Re: Vivado 2019.1 IOBUF changes vs. 2018.7 or upgrade problems?

That would be fantastic. It is part of a larger project "GXSM", what actually is open source, the current Verilog files are here and you should in general be able to "bootstrap" a complete project with thos files:

https://sourceforge.net/p/gxsm/svn/HEAD/tree/trunk/Gxsm-3.0/plug-ins/control/RedPitaya-Support/RedPACPLL4.srcs/

this is the testbed (what created the output seen in tehscreenshot above) for the "io-connect" functions:

McBSP_tb.v

This is simply providing the "pin connectivity" I need and I do have the issue with since upgrading:

McBSP_io_connect.v

used by the serial controller module (providing a high speed real time serial link to a external DSP system...)

McBSP_controller.v

I did not went further with the simulation here. I know and see the other main FPGA functionality (PAC-PLL) working just fine.

-Py

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Teacher drjohnsmith
Teacher
471 Views
Registered: ‎07-09-2009

Re: Vivado 2019.1 IOBUF changes vs. 2018.7 or upgrade problems?

Sorry, I assumed you had a smaller build than that,
as its a rediyta project, you might want to try the project site
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Visitor pyzahl
Visitor
439 Views
Registered: ‎02-26-2018

Re: Vivado 2019.1 IOBUF changes vs. 2018.7 or upgrade problems?

Hello, thanks anyways for the offer. I doubt they can help, as the FPGA implementaion or design is from ground up my own design. Nothing left from the RedPitaya's original FPGA implementaion besides the AD/DA support and basic system/pin assignmnet parts.

May be you can just have a look at this particular simple code what does no more than providing a module to access the pin "data":

https://sourceforge.net/p/gxsm/svn/HEAD/tree/trunk/Gxsm-3.0/plug-ins/control/RedPitaya-Support/RedPACPLL4.srcs/McBSP_io_connect.v

 

thnanks

-Py

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Teacher drjohnsmith
Teacher
411 Views
Registered: ‎07-09-2009

Re: Vivado 2019.1 IOBUF changes vs. 2018.7 or upgrade problems?

that looks great

Just check you have that module as a top level module, directly connecting to the IO pins
<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
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