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rwnbiad
Newbie
Newbie
7,042 Views
Registered: ‎04-02-2016

Vivado Placement Error [Place 30-675]

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I have a problems for PnR with vivado

Input port for my top module "JTCK_dsp" is not placed global clock-capabel pin. I just connect the port to sub-module.

I tried to insert "set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets JTCK_dsp_IBUF]" to my .xdc, but this error isn't cleared.

=====================================================

ERROR: [Place 30-675] Sub-optimal placement for a global clock-capable IO pin and BUFG pair.If this sub optimal condition is acceptable for this design, you may use the CLOCK_DEDICATED_ROUTE constraint in the .xdc file to demote this message to a WARNING. However, the use of this override is highly discouraged. These examples can be used directly in the .xdc file to override this clock rule.
        < set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets JTCK_dsp_IBUF] >

        JTCK_dsp_IBUF_inst/IBUFCTRL_INST (IBUFCTRL.O) is locked to IOB_X1Y483 (in SLR 1)
        JTCK_dsp_IBUF_BUFG_inst (BUFGCE.I) is provisionally placed by clockplacer on BUFGCE_X1Y216 (in SLR 1)

        The above error could possibly be related to other connected instances. Following is a list of
        all the related clock rules and their respective instances.

        Clock Rule: rule_bufgce_bufg_conflict
        Status: PASS
        Rule Description: Only one of the 2 available sites (BUFGCE or BUFGCE_DIV/BUFGCTRL) in a pair can be
        used at the same time
        JTCK_dsp_IBUF_BUFG_inst (BUFGCE.O) is provisionally placed by clockplacer on BUFGCE_X1Y216 (in SLR 1)

Resolution: A dedicated routing path between the two can be used if: (a) The global clock-capable IO (GCIO) is placed on a GCIO capable site (b) The BUFG is placed in the same clock region of the device as the GCIO pin. Both the above conditions must be met at the same time, else it may lead to longer and less predictable clock insertion delays.

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vemulad
Xilinx Employee
Xilinx Employee
12,869 Views
Registered: ‎09-20-2012

Hi @rwnbiad

 

Open synthesized design and run the below command from TCL console manually, see if it returns any warnings.

 

set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets JTCK_dsp_IBUF]

 

 

Thanks,
Deepika.
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3 Replies
vemulad
Xilinx Employee
Xilinx Employee
12,870 Views
Registered: ‎09-20-2012

Hi @rwnbiad

 

Open synthesized design and run the below command from TCL console manually, see if it returns any warnings.

 

set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets JTCK_dsp_IBUF]

 

 

Thanks,
Deepika.
--------------------------------------------------------------------------------------------
Google your question before posting. If someone's post answers your question, mark the post as answer with "Accept as solution". If you see a particularly good and informative post, consider giving it Kudos (the star on the left)

View solution in original post

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mik3l3_hdl
Participant
Participant
614 Views
Registered: ‎08-15-2019

Hi,

 

i got a similar error.


So the culprit is that the Clock and the BUFG are not in the same clock region.

1) when assigning constraints how i can understand in which clock region is located the pin selected for a specific constraint?

 

2) what are the BUFG and how i can understand if a port is a BUFG? (I cannot see anywhere the acronym BUFG in my design)

 

Thanks
Regards

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rshekhaw
Xilinx Employee
Xilinx Employee
588 Views
Registered: ‎05-22-2018

Hi @mik3l3_hdl ,

As your queries are different, please create a new post.

Thanks,

Raj

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