cancel
Showing results for 
Search instead for 
Did you mean: 
Highlighted
982 Views
Registered: ‎09-10-2018

[Vivado][implementation][IOCNT-2] avoid mapping ports to FPGA I/Os

Jump to solution

Hi

 

I am sure its a very basic and a common problem.

 

I am working a module of a larger FPGA design. I just want to test the performance and resource utilization of my module. When I tried to synthesize and run implementation, I got the following error:

 

[Drc 23-20] Rule violation (IOCNT-2) Number of HP/HR IOs - The design contains 1027 unplaced High Range-only I/O ports while the target device, xc7z010clg400-3, has 100 remaining available High Range I/O pins. To correct this issue:
1. Ensure you are targeting the correct device and package. Select a larger device or different package if necessary.
2. Check the top-level ports of the design to ensure the correct number of ports are specified.
3. Consider design changes to reduce the number of High Range I/O pins needed.
 
Is there a way to avoid port mapping to FPGA IOs while at the same time avoid any sort of optimization due to 'unconnected' logic?
 
for setup and hold timing analysis, I made sure to flop all the inputs and outputs.
 
Thank you for your precious time
0 Kudos
1 Solution

Accepted Solutions
Highlighted
Xilinx Employee
Xilinx Employee
954 Views
Registered: ‎05-08-2012

Re: [Vivado][implementation][IOCNT-2] avoid mapping ports to FPGA I/Os

Jump to solution

Hi @ali.digitekeng. The placer is required to place I/O ports where buffers are connected. One way to avoid the issue would be to disable the I/O buffer insertion using the IO_BUFFER_TYPE property.

 

set_property IO_BUFFER_TYPE none [get_ports <port_name>]

 

http://www.xilinx.com/support/documentation/sw_manuals/xilinx2017_4/ug912-vivado-properties.pdf#page=224

 

Also available is the out of context flow. This would normally be used as a piece of a larger design. Information on this can be found in the Hierarchical Design Guide. There are specific commands and properties required.

 

http://www.xilinx.com/support/documentation/sw_manuals/xilinx2017_4/ug905-vivado-hierarchical-design.pdf#page=9

-------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------

---------------------------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
---------------------------------------------------------------------------------------------

View solution in original post

2 Replies
Highlighted
Xilinx Employee
Xilinx Employee
955 Views
Registered: ‎05-08-2012

Re: [Vivado][implementation][IOCNT-2] avoid mapping ports to FPGA I/Os

Jump to solution

Hi @ali.digitekeng. The placer is required to place I/O ports where buffers are connected. One way to avoid the issue would be to disable the I/O buffer insertion using the IO_BUFFER_TYPE property.

 

set_property IO_BUFFER_TYPE none [get_ports <port_name>]

 

http://www.xilinx.com/support/documentation/sw_manuals/xilinx2017_4/ug912-vivado-properties.pdf#page=224

 

Also available is the out of context flow. This would normally be used as a piece of a larger design. Information on this can be found in the Hierarchical Design Guide. There are specific commands and properties required.

 

http://www.xilinx.com/support/documentation/sw_manuals/xilinx2017_4/ug905-vivado-hierarchical-design.pdf#page=9

-------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------

---------------------------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
---------------------------------------------------------------------------------------------

View solution in original post

Highlighted
944 Views
Registered: ‎09-10-2018

Re: [Vivado][implementation][IOCNT-2] avoid mapping ports to FPGA I/Os

Jump to solution
Thanks marcb. I used 'out of context' based solution as my module is definitely part of a larger design and I just want to make sure my module is well under resource cap
0 Kudos