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gandesiri_ql
Visitor
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Registered: ‎10-02-2014

Vivado v2014.3 -- ERROR: [Drc 23-20] Rule violation (UCIO-1) Unconstrained Logical Port

With Vivado 2014.3 we are seeing this DRC error, which we did not see in 2013 version.

 

10084:ERROR: [Drc 23-20] Rule violation (UCIO-1) Unconstrained Logical Port - 4 out of 74 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined. To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: BF_CLK, BF_NSS, BF_MOSI, BF_MISO.

 

We have the following physical constraints given to the design, but still see the above error

set_property PACKAGE_PIN AL31 [get_ports BF_CLK]
set_property PACKAGE_PIN AM31 [get_ports BF_NSS]
set_property PACKAGE_PIN AL30 [get_ports BF_MISO]
set_property PACKAGE_PIN AL29 [get_ports BF_MOSI]

set_property IOB TRUE [get_ports {BF_CLK}]
set_property IOB TRUE [get_ports {BF_NSS}]
set_property IOB TRUE [get_ports {BF_MOSI}]
set_property IOB TRUE [get_ports {BF_MISO}]

 

Any IDEA?

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21 Replies
mcgett
Xilinx Employee
Xilinx Employee
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Registered: ‎01-03-2008

Something must have happened with your project when you upgraded and the XDC constraints are no longer being applied.

------Have you tried typing your question into Google? If not you should before posting.
Too many results? Try adding site:www.xilinx.com
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gandesiri_ql
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Registered: ‎10-02-2014

I cleaned everything and ran a fresh project. Still seeing the same issue. I ran in multiple folders, but still see the same error.

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gandesiri_ql
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Registered: ‎10-02-2014

rm -rf *.dcp vivado* *.cache *.runs *.xpr *.log

 

Anything else need to cleanup apart from above?

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vemulad
Xilinx Employee
Xilinx Employee
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Registered: ‎09-20-2012

Hi,

Did you see any critical warnings related to the constraints during synthesis/implementation?

Can you attach runme.log files located in synth_1 and impl_1 folders of .runs directory here? Also attach the xdc file.

Thanks,
Deepika.
Thanks,
Deepika.
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gandesiri_ql
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I dont see any critial warnings, it says 0 critical warnings. I cannot post the log file or xdc in this forum. If you work for Xilinx, I can email you, provided you give me your email address.

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gandesiri_ql
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Registered: ‎10-02-2014

set_property IOSTANDARD LVCMOS18 [get_ports {BF_*}]

set_property PACKAGE_PIN AL31 [get_ports BF_CLK]
set_property PACKAGE_PIN AM31 [get_ports BF_NSS]
set_property PACKAGE_PIN AL30 [get_ports BF_MISO]
set_property PACKAGE_PIN AL29 [get_ports BF_MOSI]

set_property IOB TRUE [get_ports {BF_CLK}]
set_property IOB TRUE [get_ports {BF_NSS}]
set_property IOB TRUE [get_ports {BF_MOSI}]
set_property IOB TRUE [get_ports {BF_MISO}]
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vemulad
Xilinx Employee
Xilinx Employee
17,972 Views
Registered: ‎09-20-2012

Hi,

 

I have recieved the log files.

 

I see no references to the physical_constraints.xdc in the implementation runme.log file.

 

Can you check if the "used in" property of XDC is set as both synthesis and implementation in XDC file properties?

 

Also in the implementated design can you see if the LOC constraints specified in XDC are obeyed or not?

 

Thanks,

Deepika.

Thanks,
Deepika.
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gandesiri_ql
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Registered: ‎10-02-2014

Can you check if the "used in" property of XDC is set as both synthesis and implementation in XDC file properties?

Yes it is checked for both syn and impl.

 

Also in the implementated design can you see if the LOC constraints specified in XDC are obeyed or not?

Yes, they are obeyed. It is giving this issue for 4 ports out of 84, so it should have taken it.

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akash_0406
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Registered: ‎10-07-2013

Hi 

I am seeing the same issue with 2014.3, it used work fine with 2014.2

 

UCIO-1#1 Critical Warning
Unconstrained Logical Port
267 out of 267 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined. To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: DDR3_A[14:0], DDR3_BA[2:0], DDR3_D[63:0], DDR3_DQS_P[7:0], DDR3_DQS_N[7:0], DDR3_DM[7:0], FLASH_A[26:0], FLASH_D[15:0], PCIE_RX_P[3:0], PCIE_RX_N[3:0], PCIE_TX_P[3:0], PCIE_TX_N[3:0], VLINK_RDATP[5], VLINK_RDATP[4], VLINK_RDATP[2] (the first 15 of 99 listed).
Related violations: <none>

 

I verified that pins are assigned by opening vivado in tcl mode:

 

Vivado% get_property PACKAGE_PIN [get_ports VLINK_RDATP[2]]
B6
Vivado% get_property PACKAGE_PIN [get_ports VLINK_RDATP[4]]
T6

Vivado% get_property PACKAGE_PIN [get_ports DDR3_A[0]]
AH12
Vivado% get_property PACKAGE_PIN [get_ports DDR3_A[14]]
AK10

 

Attached here is the *pins.tcl file I was using

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gandesiri_ql
Visitor
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Registered: ‎10-02-2014

Yes, the new version sucks and the xilinx support is awful :). I have been asking them to open a webcase (as we dont have a ability to it) dont see any positive response.

 

 

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eric@janteq
Observer
Observer
14,538 Views
Registered: ‎10-24-2014

I am working on xapp592, 4 channel sdi demo. it ends up with this error either, it show 59 out of 63 .... no idea why 2014.3 has this problem, very easy to reproduce

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eric@janteq
Observer
Observer
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Registered: ‎10-24-2014

the only thing i can do now is overide this error to let the tools generate the bitstream, but will it damage the part?

set_property SEVERITY {Warning} [get_drc_checks UCIO-1]

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eric@janteq
Observer
Observer
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Registered: ‎10-24-2014

also, i have tested with the 2014.2, looks like does not have this issue.

 

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vemulad
Xilinx Employee
Xilinx Employee
14,455 Views
Registered: ‎09-20-2012

Hi,

 

I have recently seen this issue with one of the designs. When I changed the XDC file "used in" property to include "opt_design" as shown below, the issue is solved. See if this helps.

 

Untitled.png

 

Thanks,

Deepika.

Thanks,
Deepika.
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gandesiri_ql
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Which phase are you seeing this error? Is it implemenation or Bitstream?

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gandesiri_ql
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At what phase are you seeing the error?
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zhangwei0814
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Registered: ‎10-08-2014

Hi 

       The ISE synthesis and implementation are true, finally  resource utilization analysis report is normal. Now in the Vivado,  in the first step(Implementation) to realize the logic optimization (opt_design) put a lot of resources to optimize away the module (suggests logical unit not load), but when the ISE implementation has not been optimized away, now  how to ensure the logic module resources are not optimized  in the  Vivado implementation stage?

      Now in vivado 2014.2 , the synthesized design the connectivity of the elements getting trimmed is proper.So synthesis is normal,resource utilization is also normal .However ,in the implementation phase,most of the resources are optimized away and resource utilization is not normal .I can't achive desired functionality with the optimized design because of losing too much ogic modules .I want to know how to solve the problem for ensuring the logic module resources are not optimized in the Vivado implementation stage?

      The following two picture indicata the resource utilization.

      Thanks.

D74`_NVXD1@EHR]LZKB]P}I.jpg
6TL}OD[HYO(TZWP6VSRN83U.jpg
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vemulad
Xilinx Employee
Xilinx Employee
14,397 Views
Registered: ‎09-20-2012

Hi wei zhang,

 

Dont mix up different issues in a single thread.

 

Please post your query in new thread.

 

Thanks,

Deepika.

Thanks,
Deepika.
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vemulad
Xilinx Employee
Xilinx Employee
14,394 Views
Registered: ‎09-20-2012

Hi @gandesiri_ql 

 

I did not get your last post. In the issue which I mentioned in my earlier post, the error is seen at bitgen.

 

Thanks,

Deepika.

Thanks,
Deepika.
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gandesiri_ql
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Registered: ‎10-02-2014

I tried like this as you said

 

set_property USED_IN {synthesis implementation opt_design}

 

 

but did not work and it was still failing at bitgen so I tried like this and it worked.

set_property USED_IN {synthesis implementation opt_design write_bitstream write_bitstream_post}

 

Can you telll us what does the extra two options two?

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eric@janteq
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Observer
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Registered: ‎10-24-2014

confirm 

 

set_property USED_IN {synthesis implementation opt_design write_bitstream write_bitstream_post}

 

works.

 

have not tried  set_property USED_IN {synthesis implementation opt_design}

 

 

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