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Contributor
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Registered: ‎09-20-2018

Vivado xdc case sensitivity

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Vivado xdc rules are case sensitive.

I have a port named 'IIC_0' which is constrained as

 

set_property PACKAGE_PIN E18 [get_ports iic_0_scl_io]

Vivado 2016.4 is recognizing it properly, yet

Vivado 2017.4 is not.

 

Since xdc are case sensitive, why is it not resulting in an unfeasible IO placement error in 2016.4 with VHDL RTL ports and xdc rules that do not match letter case (as seen in Vivado 2017.4)?

 

Environment: Ubuntu 16.04

Vivado: 2016.4, 2017.4

Project configuration: project mode, target language: VHDL

 

--------------------

edit: both are case sensitive. In Vivado 2017.4 pin name must match letter case of VHDL RTL code. In Vivado 2016.4 pin name must be lowercase.

 

set_property PACKAGE_PIN E18 [get_ports IIC_0_scl_io]

Vivado 2017.4 is recognizing it properly, yet

Vivado 2016.4 is not.

 

What could be causing the difference?

--------------------

 

thank you

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Contributor
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Registered: ‎09-20-2018

@syedz,

 

Thank you for your reply. I see now that xdc respects letter casing for both versions. The problem was that Vivado generates different RTL wrapper for the same block design:

 

RTL wrapper.png

 

to the left you can see the block design in question, in the middle the generated output from Vivado 2016.4 and to the right respective output from Vivado 2017.4. Note the different output for the port 'IIC_0'.

 

This has to be taken into consideration when upgrading a hardware design from 2016.4.

 

Do you have an migrating Vivado guide?

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Registered: ‎01-16-2013

@jack.roundhouse

 

Yes, you are right. XDC is case sensitive and the name should exactly match to the case letter in RTL. I checked in Vivado 2018.1

Capture.JPG

 

--Syed

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Contributor
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Registered: ‎09-20-2018

@syedz,

 

Thank you for your reply. I see now that xdc respects letter casing for both versions. The problem was that Vivado generates different RTL wrapper for the same block design:

 

RTL wrapper.png

 

to the left you can see the block design in question, in the middle the generated output from Vivado 2016.4 and to the right respective output from Vivado 2017.4. Note the different output for the port 'IIC_0'.

 

This has to be taken into consideration when upgrading a hardware design from 2016.4.

 

Do you have an migrating Vivado guide?

View solution in original post

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Registered: ‎01-22-2015

@jack.roundhouse

 

Good catch!

 

-and just to keep everyone on their toes, VHDL is not case sensitive.

 

Mark

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Registered: ‎01-08-2012

-and just to keep everyone on the very tips of their toes, VHDL is not case sensitive most of the time.

 

From the 2008 VHDL LRM, section 15.4.2 Basic Identifiers

... Basic identifiers differing only in the use of corresponding uppercase and lowercase letters are considered the same.

Section 15.4.3 Extended Identifiers

... Extended identifiers differing only in the user of corresponding uppercase and lowercase letters are distinct.

 

We typically don't use extended identifiers often, except when handing designs imported from other languages with different rules regarding valid identifiers e.g. EDIF from a schematic for a PCB that we're simulating.  Extended identifiers are the ones inside \ \ characters that allow any graphic_character (including spaces) to be used as part of the name.

 

Other exceptions to case insensitivity in VHDL:

 

- Labels (e.g. for instantiations, blocks, generates, etc.) may be compiled (into e.g. EDIF or other netlist) with the original case they had in the source code.  This means that case-sensitive downstream processing (e.g. when matching constraints) may also have to use the same case as the VHDL source.

The LRM doesn't say either way (see Edit, below) but I have observed that some compilers will convert labels to lower case, and others will keep the original case from the source code.

BTW, Our internal coding guidelines say to make all labels lower case in the source code, to avoid portability issues.

 

- LRM section 15.8: the base_specifier for a bit string literal must be in uppercase.  E.g. X"ffff" is equivalent to the string "1111111111111111", but x"ffff" is a syntax error.

 

 

EDIT: I just read (Annex C, Syntax Summary, 11.8) that labels are identifiers, and (basic) identifiers are case insensitive, as far as VHDL is concerned.  (That doesn't say anything about the generated netlist, however.)

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Registered: ‎09-20-2018

@allanherriman,

 

This is all widely known about VHDL. A case insensitive language is not necessarily insensitive to consistency. The issue here is not case sensitivity of VHDL or xdc. XDC has to match letter case of VHDL ports.

 

When upgrading Vivado 2016.4 letter case may no longer match. The problem here is that this is not widely known. We make all port names uppercase and therefore, all XDC files have to be adjusted, once for Vivado 2016.4 and once when upgrading.

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