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sanhu
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Registered: ‎12-04-2014

Why vivado cannot find gtp clock when implementation but can find gtp clock when timing analysis

I have a design which has cross clock logic . signals driven by a clock and then feed to aurora clock . The route runs for a long time because vivado cross clock logic has a large slack . to avoid this , I set the clock and aurora clock as asynchrous clock in .xdc file . meanwhile , i set false path between to clocks . but vivado report the aurora clock cannot be found when implementation . what may be the problem ? 

software : vivado 2016.2 

devices  : artix7-50

 

attachment is implementation waning and timing report

 

QQ图片20171121224516.jpg
QQ图片20171121224508.jpg
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jmcclusk
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Registered: ‎02-24-2014

Run the Clock Interaction Timing Report, and then you should be able to see the clock domain crossings (CDC) to your aurora clock..  Once you find it,  click on the square, and it will show the timing in the list below..   If it's a timed path with an impossible requirement (like 1 or 2 ns), then right click on the square, and select "set maximum delay"   Set your max delay constraint to be equal to the minimum of the TX and RX clock periods on the CDC as a starting point.   I don't recommend using "set false path" or "set clocks asynchronous".     There's a much deeper discussion to be had about using XPM_CDC components on all your clock crossings, but this should get you started, provided that you've properly put in a dual clock fifo to cross the CDC boundaries.

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sanhu
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Registered: ‎12-04-2014

In Clock Interaction Timing Report , it is displayed as partial ignored path . I tried right click the path and set false path , save to .xdc file . But vivado still can not find the aurora clock when implementation .

 

These cross clock signals are some registers vary only at design initial process . In aurora clock domain , they can be treated as constant . so there are no need to check timing requirement between then . as set_false_path and set_asynchronous_clock are both failed , vivado check timing between two clock and lead to a long run when routing .

 

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jmcclusk
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Registered: ‎02-24-2014

It sounds like the paths or clock might have been removed during design optimization..   are you running the clock interaction report on the synthesized design?  or the implemented design.    Stuff can go missing between these two stages.

Don't forget to close a thread when possible by accepting a post as a solution.
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sanhu
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Registered: ‎12-04-2014

i have run clock interaction on synthesised desin and the cross clock path does exist and is displayed as user ignored safe path .
but in implementaion design initialization process, vivado report critical warning that no valid object found for aurora clock which leads to long run.
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