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Visitor linofex
Visitor
280 Views
Registered: ‎12-14-2018

Why worst negative slack is reduced after implementation?

Hi, during the Synthesis phase I get a WNS that is 7.043ns. After the implementation, the WSN is slightly less = 6.969ns.
I only set the clock constraint at 100MHz, no more, even pin assignment, just synthesis and implementation.

It is a little project with a register + combinational logic + register.

I would ask why this reduction (and moreover the path changes)? 
I'm thinking it depends that during the synthesis vivado "try" to guess the value and then during the implementation it actually measure it.

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4 Replies
Xilinx Employee
Xilinx Employee
265 Views
Registered: ‎05-08-2012

Re: Why worst negative slack is reduced after implementation?

Hi @linofex.

The post-synthesis timing is using estimated values for delays. At this point, there is no placement or routing information, so delay estimates are used. Once Implementation completes, the actual routing delays are reported. Hope this helps.

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Visitor linofex
Visitor
259 Views
Registered: ‎12-14-2018

Re: Why worst negative slack is reduced after implementation?

Hi, thanks for the quick reply. So the real values are the after-implementation values and I  should use them to compute some other values like max operating frequency, right?

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Scholar watari
Scholar
187 Views
Registered: ‎06-16-2013

Re: Why worst negative slack is reduced after implementation?

Hi @linofex

 

After synthesis, EDA tool (Vivado) estimates path delay and maximum frequency with temporal path delay.

Because of design doesn't finish place and route by it.

 

After place & route, tool can estimate and calculate path delay and maximum operating frequency with real placement information.

It means design can achieve maximum operating frequency with guaranty.

 

So, in this case, your understanding is correct.

 

Best regards,

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Voyager
Voyager
158 Views
Registered: ‎10-23-2018

Re: Why worst negative slack is reduced after implementation?

@linofex

Another possible reason that implementation reduces negative slack... it the LUT is not shared, the routing can be shorter... so depending on your settings and strategy the resources and routing can be different.

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