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Observer tollinjose
Observer
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Will BUFGCE get optimized to FDCE ?

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For a simple logic implementation of clock gating I used BUFGCE. When went through the schematics I noticed logic is implemented using FDCEs. But CE of FDCE are not used. My question is why BUFGCE didn't got optimized using CE in FDCE. Am I missing something here ? Please help.

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Xilinx Employee
Xilinx Employee
1,615 Views

Re: Will BUFGCE get optimized to FDCE ?

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BUFGCE is a clock buffer with one clock input, one clock output and a clock enable line. FDCE is D Flip-Flop with Clock Enable and Asynchronous Clear.  BUFGCE cannot be optimized using CE in FDCE. 

Check these library guides for details 

https://www.xilinx.com/support/documentation/sw_manuals/xilinx13_2/7series_scm.pdf

https://www.xilinx.com/support/documentation/user_guides/ug362.pdf

 

--Example non gated clock 

 

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity normalclk is
port( clk : in std_logic;
      load : in std_logic;
      i : in std_logic;
     o : out std_logic
      );     
end normalclk;


architecture Behavioral of normalclk is

BEGIN
process(clk)
begin
if(rising_edge(clk)) then
if(load ='1') then
<= i;
end if;
end if;
end process;

end Behavioral;

 

--VHDL code for gated clock

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity gatedclk is
port( clk : in std_logic;
      load : in std_logic;
      i : in std_logic;
      o : out std_logic
      );     
end gatedclk;

architecture Behavioral of gatedclk is
signal gclk : std_logic;

BEGIN
gclk <= clk and load;
process(gclk)
begin
if(rising_edge(gclk)) then
o <= i;
end if;
end process;

end Behavioral;

Thanks and Regards
Balkrishan
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4 Replies
Moderator
Moderator
1,080 Views

Re: Will BUFGCE get optimized to FDCE ?

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@tollinjose,

 

Are you using instantiation of BUFGCE? If yes, then it will not be optimized to FDCE. 

Can you share the snippet of code and its schematic?

 

--Syed

---------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.

Did you check our new quick reference timing closure guide (UG1292)?
---------------------------------------------------------------------------------------------
Xilinx Employee
Xilinx Employee
1,616 Views

Re: Will BUFGCE get optimized to FDCE ?

Jump to solution

BUFGCE is a clock buffer with one clock input, one clock output and a clock enable line. FDCE is D Flip-Flop with Clock Enable and Asynchronous Clear.  BUFGCE cannot be optimized using CE in FDCE. 

Check these library guides for details 

https://www.xilinx.com/support/documentation/sw_manuals/xilinx13_2/7series_scm.pdf

https://www.xilinx.com/support/documentation/user_guides/ug362.pdf

 

--Example non gated clock 

 

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity normalclk is
port( clk : in std_logic;
      load : in std_logic;
      i : in std_logic;
     o : out std_logic
      );     
end normalclk;


architecture Behavioral of normalclk is

BEGIN
process(clk)
begin
if(rising_edge(clk)) then
if(load ='1') then
<= i;
end if;
end if;
end process;

end Behavioral;

 

--VHDL code for gated clock

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity gatedclk is
port( clk : in std_logic;
      load : in std_logic;
      i : in std_logic;
      o : out std_logic
      );     
end gatedclk;

architecture Behavioral of gatedclk is
signal gclk : std_logic;

BEGIN
gclk <= clk and load;
process(gclk)
begin
if(rising_edge(gclk)) then
o <= i;
end if;
end process;

end Behavioral;

Thanks and Regards
Balkrishan
--------------------------------------------------------------------------------------------
Please mark the post as an answer "Accept as solution" in case it helped resolve your query.
Give kudos in case a post in case it guided to the solution.
Observer tollinjose
Observer
1,042 Views

Re: Will BUFGCE get optimized to FDCE ?

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yes. I was using instantiation of BUFGE. My circuit was very simple, I just implemented a simple four bit counter to which I gave clock through BUFGCE. You meant once we instantiate its hard wired? Optimization algorithm of xilinx wont touch it ? 

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Moderator
Moderator
1,035 Views

Re: Will BUFGCE get optimized to FDCE ?

Jump to solution

@tollinjose,

 

 You meant once we instantiate its hard wired? Optimization algorithm of xilinx wont touch it ? 

As per my knowledge Yes. 

 

Regards,
Syed

---------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.

Did you check our new quick reference timing closure guide (UG1292)?
---------------------------------------------------------------------------------------------
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