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Observer gurkirat
Observer
930 Views
Registered: ‎07-27-2010

With Vivado 2018.3 start getting DRC AVAL-245 error during Bit Generation

I start seeing DRC error during Bit generation phase with recent 2018.3 Vivado compile. The error message is shown in the bottom. Basically I used Async FIFO(independent clock fifo)  as common clock fifo. This implementation used to work before Vivado 2018.3 but start failling with this version. 

I wonder if there is any kind of patch avilable for this error, or anybodey else seen this issue.

ERROR: [DRC AVAL-245] Independent_clock_check: The RAMB36E2 cell */../..//U_DP_RAM36x2K_C/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/prim_noinit.ram/DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram has CLOCK_DOMAINS=INDEPENDENT. However the two clock pins, CLKARDCLK and CLKBWRCLK, are driven by the same driver. The expected property value for CLOCK_DOMAINS for this clocking connectivity is COMMON. Improperly setting this attribute can impact simulation, optimization, and timing for the RAM resulting in incorrect simulation behavior, potential loss of performance, and increase in power.

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10 Replies
Moderator
Moderator
875 Views
Registered: ‎01-16-2013

Re: With Vivado 2018.3 start getting DRC AVAL-245 error during Bit Generation

@gurkirat

 

The error message is self-explanatory. Open the synthesized or implemented design and search of the cell mentioned in error message:

show_objects [get_cells */../..//U_DP_RAM36x2K_C/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/prim_noinit.ram/DEVICE_8SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram]

 

Click on on the RAM36E2 cells and check its properties. You should see CLOCK_DOMAINS=INDEPENDENT. 

Now check the cells pins "CLKARDCLK and CLKBWRCLK, are driven by the same driver"

 

If they are from same driver then in cell properties change CLOCK_DOMAINS to COMMON. 

 

This implementation used to work before Vivado 2018.3 but start failling with this version. 

Compare the schematic and properties of the cell in passing and failing version. Check for any optimization messages in 2018.3

 

--Syed

--Syed

 

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Observer gurkirat
Observer
858 Views
Registered: ‎07-27-2010

Re: With Vivado 2018.3 start getting DRC AVAL-245 error during Bit Generation

Thanks Syedz.

We have this old IP code which has number of Block RAMs , xilinx generated cores. In this code , the cores are generated with independent-clock setting, but in some cases same clock is used on both sides. So far, pre to Vivado 2018.3 , this implementation was not creating this kind of error message or issue. At this point, I do not want to change the code but trying to find if something is changed in the recent vivado release and if there is any work around available.

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Moderator
Moderator
786 Views
Registered: ‎01-16-2013

Re: With Vivado 2018.3 start getting DRC AVAL-245 error during Bit Generation

@gurkirat

 

You can compare the schematics of the problematic cells mentioned in error message with passing and failing build. 
Also, check for any information message in Vivado.log file.

 

--Syed

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Observer czeck
Observer
719 Views
Registered: ‎08-28-2017

Re: With Vivado 2018.3 start getting DRC AVAL-245 error during Bit Generation

Are there any work-arounds for this issue. 

I am using 3rd party IP which I cannot change and I cannot add additional clocks as work-around.

Thanks,

 

 

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Observer new_user
Observer
700 Views
Registered: ‎12-29-2016

Re: With Vivado 2018.3 start getting DRC AVAL-245 error during Bit Generation

You can right-click on the error message and suppress it.

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Xilinx Employee
Xilinx Employee
689 Views
Registered: ‎05-08-2012

Re: With Vivado 2018.3 start getting DRC AVAL-245 error during Bit Generation

Hi @gurkirat 

In order to identify a workaround, the Vivado stage that is different with 2018.3 would have to be identified. This means comparing the connecitivity and property values at different stages. I would start with a post-synthesis view and determine if this violates the DRC. Since the AVAL-245 DRC is in the BITSTREAM ruledeck, you could run report_drc and add the bitstream DRC ruledeck for this report.

If the post-synthesis netlist violates the DRC, I would open the elaborated design to see what the properties and connectivity is. If not, the implementation stages should be checked. With the step identified, you can look at the log for this step to see if there are messages concerning this change.


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Moderator
Moderator
674 Views
Registered: ‎01-16-2013

Re: With Vivado 2018.3 start getting DRC AVAL-245 error during Bit Generation

@gurkirat 

 

Any update on this thread?

 

--Syed

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Observer czeck
Observer
644 Views
Registered: ‎08-28-2017

Re: With Vivado 2018.3 start getting DRC AVAL-245 error during Bit Generation

I generated (from the error messages) a list of the cell with the DRC violation and set properties as follows in the post-synth stage.

set_property CLOCK_DOMAINS COMMON [get_cells xx/xxx/]

That worked for me.

 

I was not able to work-around this problem using:

set_property SEVERITY {Warning} [get_drc_checks AVAL-245]

 

 

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Observer gurkirat
Observer
637 Views
Registered: ‎07-27-2010

Re: With Vivado 2018.3 start getting DRC AVAL-245 error during Bit Generation

Thanks Czeck. 

                   I also solved this problem modifying the core  by setting the COLCK_DOMAIN to Common, which I was trying to avoid. I never find the answer why they changed in the recent Vivado.  

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Moderator
Moderator
585 Views
Registered: ‎01-16-2013

Re: With Vivado 2018.3 start getting DRC AVAL-245 error during Bit Generation

@gurkirat 

 

Can you please close this thread by marking the helpful post as "Accept as solution"

 

-_Syed

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