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Adventurer
Adventurer
348 Views
Registered: ‎10-18-2017

Zynq UltraScale+: [Place 30-99] Placer failed with error: 'IO Clock Placer failed'

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 I have looked at the post https://forums.xilinx.com/t5/Implementation/IO-clock-placer-failed-when-my-project-run-the-imeplementation/m-p/903654#M22799, and am having a similar issue.

Unlike that post, I have a clock rule that is failing. Clock Rule: rule_bufds_gthchannel_intelligent_pin. I am not sure what this rule means, or how to correct it. Would it be wise to use the suggested workaround in a constraints file or would that ruin my design?

Another issue I am having, although I am not sure if it is related, is that I am getting an error 

[BD 41-758] The following clock pins are not connected to a valid clock source:
/v_hdmi_tx_ss_0/s_axis_audio_aclk

In my design, I am only trying to send video to the HDMI Transmitter core without audio. I have looked at an example design where they do the same thing, and they have the audio clock wired as shown below.

 

video_design.pngThat clock then goes over to the UltraScale+ block to a pl_clk at 300MHz. Note that the AXI Lite Clocks are at 100MHz in the design. 

The above error is listed under "General Messages"

Here is the log file for the placing error itself

[Place 30-739] Sub-optimal placement for an IBUFDS_GT / GT component pair.If this sub optimal condition is acceptable for this design, you may use the CLOCK_DEDICATED_ROUTE constraint in the .xdc file to demote this message to a WARNING. However, the use of this override is highly discouraged. These examples can be used directly in the .xdc file to override this clock rule.
< set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets design_1_i/vid_phy_controller_0/inst/gt_usrclk_source_inst/gtrefclk1_in[0]] >

design_1_i/vid_phy_controller_0/inst/gt_usrclk_source_inst/IBUFDS_GTE4_MGTREFCLK1_INST (IBUFDS_GTE4.O) is locked to GTHE4_COMMON_X0Y4
design_1_i/vid_phy_controller_0/inst/gt_common_inst/common_inst/gthe4_common_gen.GTHE4_COMMON_PRIM_INST (GTHE4_COMMON.GTREFCLK10) is provisionally placed by clockplacer on GTHE4_COMMON_X0Y0

The above error could possibly be related to other connected instances. Following is a list of
all the related clock rules and their respective instances.

Clock Rule: rule_gthcommon_gthchannel
Status: PASS
Rule Description: A GTHCommon driving a GTHChannel must both be in the same clock region
design_1_i/vid_phy_controller_0/inst/gt_common_inst/common_inst/gthe4_common_gen.GTHE4_COMMON_PRIM_INST (GTHE4_COMMON.QPLL0OUTCLK) is provisionally placed by clockplacer on GTHE4_COMMON_X0Y0
design_1_i/vid_phy_controller_0/inst/gt_wrapper_inst/inst/gen_gtwizard_gthe4_top.design_1_vid_phy_controller_0_0_gtwrapper_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST (GTHE4_CHANNEL.QPLL0CLK) is locked to GTHE4_CHANNEL_X0Y0
design_1_i/vid_phy_controller_0/inst/gt_wrapper_inst/inst/gen_gtwizard_gthe4_top.design_1_vid_phy_controller_0_0_gtwrapper_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[1].GTHE4_CHANNEL_PRIM_INST (GTHE4_CHANNEL.QPLL0CLK) is locked to GTHE4_CHANNEL_X0Y1
design_1_i/vid_phy_controller_0/inst/gt_wrapper_inst/inst/gen_gtwizard_gthe4_top.design_1_vid_phy_controller_0_0_gtwrapper_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[2].GTHE4_CHANNEL_PRIM_INST (GTHE4_CHANNEL.QPLL0CLK) is locked to GTHE4_CHANNEL_X0Y2

Clock Rule: rule_bufds_gthchannel_intelligent_pin
Status: FAIL
Rule Description: A BUFDS driving a GTHChannel must both be placed in the same or adjacent two clock
regions (top/bottom)
design_1_i/vid_phy_controller_0/inst/gt_usrclk_source_inst/IBUFDS_GTE4_MGTREFCLK1_INST (IBUFDS_GTE4.O) is locked to GTHE4_COMMON_X0Y4
design_1_i/vid_phy_controller_0/inst/gt_wrapper_inst/inst/gen_gtwizard_gthe4_top.design_1_vid_phy_controller_0_0_gtwrapper_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST (GTHE4_CHANNEL.GTREFCLK1) is locked to GTHE4_CHANNEL_X0Y0
design_1_i/vid_phy_controller_0/inst/gt_wrapper_inst/inst/gen_gtwizard_gthe4_top.design_1_vid_phy_controller_0_0_gtwrapper_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[1].GTHE4_CHANNEL_PRIM_INST (GTHE4_CHANNEL.GTREFCLK1) is locked to GTHE4_CHANNEL_X0Y1
design_1_i/vid_phy_controller_0/inst/gt_wrapper_inst/inst/gen_gtwizard_gthe4_top.design_1_vid_phy_controller_0_0_gtwrapper_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[2].GTHE4_CHANNEL_PRIM_INST (GTHE4_CHANNEL.GTREFCLK1) is locked to GTHE4_CHANNEL_X0Y2
ERROR: The above is also an illegal clock rule
Workaround: < set_property CLOCK_DEDICATED_ROUTE ANY_CMT_COLUMN [get_nets design_1_i/vid_phy_controller_0/inst/gt_usrclk_source_inst/gtrefclk1_in[0]] >

Clock Rule: rule_gt_bufggt
Status: PASS
Rule Description: A GT driving a BUFG_GT must be placed in the same clock region of the device as the
BUFG
design_1_i/vid_phy_controller_0/inst/gt_usrclk_source_inst/IBUFDS_GTE4_MGTREFCLK1_INST (IBUFDS_GTE4.ODIV2) is locked to GTHE4_COMMON_X0Y4
design_1_i/vid_phy_controller_0/inst/gt_usrclk_source_inst/bufg_gt_gtrefclk1_odiv2_inst (BUFG_GT.I) is provisionally placed by clockplacer on BUFG_GT_X0Y96

Clock Rule: rule_gtbufds_bufgsync
Status: PASS
Rule Description: A BUFDS drives a BUFG_GT_SYNC pin must both be in the same clock region and both
have to be in specific sites.
design_1_i/vid_phy_controller_0/inst/gt_usrclk_source_inst/IBUFDS_GTE4_MGTREFCLK1_INST (IBUFDS_GTE4.ODIV2) is locked to GTHE4_COMMON_X0Y4
design_1_i/vid_phy_controller_0/inst/gt_usrclk_source_inst/bufg_gt_sync_gtrefclk1_odiv2_inst (BUFG_GT_SYNC.CLK) is provisionally placed by clockplacer on BUFG_GT_SYNC_X0Y60

Clock Rule: rule_gt_bufggt
Status: PASS
Rule Description: A GT driving a BUFG_GT must be placed in the same clock region of the device as the
BUFG
design_1_i/vid_phy_controller_0/inst/gt_wrapper_inst/inst/gen_gtwizard_gthe4_top.design_1_vid_phy_controller_0_0_gtwrapper_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST (GTHE4_CHANNEL.RXOUTCLK) is locked to GTHE4_CHANNEL_X0Y0
design_1_i/vid_phy_controller_0/inst/gt_wrapper_inst/inst/gen_gtwizard_gthe4_top.design_1_vid_phy_controller_0_0_gtwrapper_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_cpll_cal_gthe4.gen_cpll_cal_inst[0].gtwizard_ultrascale_v1_7_4_gthe4_cpll_cal_inst/gtwizard_ultrascale_v1_7_4_gthe4_cpll_cal_rx_i/gen_cal_rx_en.bufg_gt_rxoutclkmon_inst (BUFG_GT.I) is provisionally placed by clockplacer on BUFG_GT_X0Y1

Clock Rule: rule_gthchannel_bufgsync_rx
Status: PASS
Rule Description: A GTHChannel drives a BUFG_GT_SYNC pin must both be in the same clock region and
both have to be in specific sites.
design_1_i/vid_phy_controller_0/inst/gt_wrapper_inst/inst/gen_gtwizard_gthe4_top.design_1_vid_phy_controller_0_0_gtwrapper_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST (GTHE4_CHANNEL.RXOUTCLK) is locked to GTHE4_CHANNEL_X0Y0
design_1_i/vid_phy_controller_0/inst/gt_wrapper_inst/inst/gen_gtwizard_gthe4_top.design_1_vid_phy_controller_0_0_gtwrapper_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/BUFG_GT_SYNC_1 (BUFG_GT_SYNC.CLK) is provisionally placed by clockplacer on BUFG_GT_SYNC_X0Y3

Clock Rule: rule_gthchannel_bufgsync_tx
Status: PASS
Rule Description: A GTHChannel drives a BUFG_GT_SYNC pin must both be in the same clock region and
both have to be in specific sites.
design_1_i/vid_phy_controller_0/inst/gt_wrapper_inst/inst/gen_gtwizard_gthe4_top.design_1_vid_phy_controller_0_0_gtwrapper_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST (GTHE4_CHANNEL.TXOUTCLK) is locked to GTHE4_CHANNEL_X0Y0
design_1_i/vid_phy_controller_0/inst/gt_wrapper_inst/inst/gen_gtwizard_gthe4_top.design_1_vid_phy_controller_0_0_gtwrapper_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/BUFG_GT_SYNC (BUFG_GT_SYNC.CLK) is provisionally placed by clockplacer on BUFG_GT_SYNC_X0Y1

Clock Rule: rule_gt_bufggt
Status: PASS
Rule Description: A GT driving a BUFG_GT must be placed in the same clock region of the device as the
BUFG
design_1_i/vid_phy_controller_0/inst/gt_wrapper_inst/inst/gen_gtwizard_gthe4_top.design_1_vid_phy_controller_0_0_gtwrapper_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[1].GTHE4_CHANNEL_PRIM_INST (GTHE4_CHANNEL.RXOUTCLK) is locked to GTHE4_CHANNEL_X0Y1
design_1_i/vid_phy_controller_0/inst/gt_wrapper_inst/inst/gen_gtwizard_gthe4_top.design_1_vid_phy_controller_0_0_gtwrapper_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_cpll_cal_gthe4.gen_cpll_cal_inst[1].gtwizard_ultrascale_v1_7_4_gthe4_cpll_cal_inst/gtwizard_ultrascale_v1_7_4_gthe4_cpll_cal_rx_i/gen_cal_rx_en.bufg_gt_rxoutclkmon_inst (BUFG_GT.I) is provisionally placed by clockplacer on BUFG_GT_X0Y3

Clock Rule: rule_gthchannel_bufgsync_rx
Status: PASS
Rule Description: A GTHChannel drives a BUFG_GT_SYNC pin must both be in the same clock region and
both have to be in specific sites.
design_1_i/vid_phy_controller_0/inst/gt_wrapper_inst/inst/gen_gtwizard_gthe4_top.design_1_vid_phy_controller_0_0_gtwrapper_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[1].GTHE4_CHANNEL_PRIM_INST (GTHE4_CHANNEL.RXOUTCLK) is locked to GTHE4_CHANNEL_X0Y1
design_1_i/vid_phy_controller_0/inst/gt_wrapper_inst/inst/gen_gtwizard_gthe4_top.design_1_vid_phy_controller_0_0_gtwrapper_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/BUFG_GT_SYNC_2 (BUFG_GT_SYNC.CLK) is provisionally placed by clockplacer on BUFG_GT_SYNC_X0Y4

Clock Rule: rule_gthchannel_bufgsync_tx
Status: PASS
Rule Description: A GTHChannel drives a BUFG_GT_SYNC pin must both be in the same clock region and
both have to be in specific sites.
design_1_i/vid_phy_controller_0/inst/gt_wrapper_inst/inst/gen_gtwizard_gthe4_top.design_1_vid_phy_controller_0_0_gtwrapper_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[1].GTHE4_CHANNEL_PRIM_INST (GTHE4_CHANNEL.TXOUTCLK) is locked to GTHE4_CHANNEL_X0Y1
design_1_i/vid_phy_controller_0/inst/gt_wrapper_inst/inst/gen_gtwizard_gthe4_top.design_1_vid_phy_controller_0_0_gtwrapper_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/BUFG_GT_SYNC_3 (BUFG_GT_SYNC.CLK) is provisionally placed by clockplacer on BUFG_GT_SYNC_X0Y2

Clock Rule: rule_gt_bufggt
Status: PASS
Rule Description: A GT driving a BUFG_GT must be placed in the same clock region of the device as the
BUFG
design_1_i/vid_phy_controller_0/inst/gt_wrapper_inst/inst/gen_gtwizard_gthe4_top.design_1_vid_phy_controller_0_0_gtwrapper_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[2].GTHE4_CHANNEL_PRIM_INST (GTHE4_CHANNEL.RXOUTCLK) is locked to GTHE4_CHANNEL_X0Y2
design_1_i/vid_phy_controller_0/inst/gt_wrapper_inst/inst/gen_gtwizard_gthe4_top.design_1_vid_phy_controller_0_0_gtwrapper_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_cpll_cal_gthe4.gen_cpll_cal_inst[2].gtwizard_ultrascale_v1_7_4_gthe4_cpll_cal_inst/gtwizard_ultrascale_v1_7_4_gthe4_cpll_cal_rx_i/gen_cal_rx_en.bufg_gt_rxoutclkmon_inst (BUFG_GT.I) is provisionally placed by clockplacer on BUFG_GT_X0Y5

Clock Rule: rule_gthchannel_bufgsync_rx
Status: PASS
Rule Description: A GTHChannel drives a BUFG_GT_SYNC pin must both be in the same clock region and
both have to be in specific sites.
design_1_i/vid_phy_controller_0/inst/gt_wrapper_inst/inst/gen_gtwizard_gthe4_top.design_1_vid_phy_controller_0_0_gtwrapper_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[2].GTHE4_CHANNEL_PRIM_INST (GTHE4_CHANNEL.RXOUTCLK) is locked to GTHE4_CHANNEL_X0Y2
design_1_i/vid_phy_controller_0/inst/gt_wrapper_inst/inst/gen_gtwizard_gthe4_top.design_1_vid_phy_controller_0_0_gtwrapper_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/BUFG_GT_SYNC_4 (BUFG_GT_SYNC.CLK) is provisionally placed by clockplacer on BUFG_GT_SYNC_X0Y10

Clock Rule: rule_gthchannel_bufgsync_tx
Status: PASS
Rule Description: A GTHChannel drives a BUFG_GT_SYNC pin must both be in the same clock region and
both have to be in specific sites.
design_1_i/vid_phy_controller_0/inst/gt_wrapper_inst/inst/gen_gtwizard_gthe4_top.design_1_vid_phy_controller_0_0_gtwrapper_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[2].GTHE4_CHANNEL_PRIM_INST (GTHE4_CHANNEL.TXOUTCLK) is locked to GTHE4_CHANNEL_X0Y2
design_1_i/vid_phy_controller_0/inst/gt_wrapper_inst/inst/gen_gtwizard_gthe4_top.design_1_vid_phy_controller_0_0_gtwrapper_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/BUFG_GT_SYNC_5 (BUFG_GT_SYNC.CLK) is provisionally placed by clockplacer on BUFG_GT_SYNC_X0Y8

Clock Rule: rule_bufgsync_bufg_withGTDriver
Status: PASS
Rule Description: A BUFG_GT_SYNC driving a BUFG_GT must be placed in the same clock region of the device
as the BUFG_GT
design_1_i/vid_phy_controller_0/inst/gt_usrclk_source_inst/bufg_gt_sync_gtrefclk1_odiv2_inst (BUFG_GT_SYNC.CESYNC) is provisionally placed by clockplacer on BUFG_GT_SYNC_X0Y60
design_1_i/vid_phy_controller_0/inst/gt_usrclk_source_inst/bufg_gt_gtrefclk1_odiv2_inst (BUFG_GT.CE) is provisionally placed by clockplacer on BUFG_GT_X0Y96

Clock Rule: rule_bufgsync_bufg_withGTDriver
Status: PASS
Rule Description: A BUFG_GT_SYNC driving a BUFG_GT must be placed in the same clock region of the device
as the BUFG_GT
design_1_i/vid_phy_controller_0/inst/gt_wrapper_inst/inst/gen_gtwizard_gthe4_top.design_1_vid_phy_controller_0_0_gtwrapper_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/BUFG_GT_SYNC_1 (BUFG_GT_SYNC.CESYNC) is provisionally placed by clockplacer on BUFG_GT_SYNC_X0Y3
design_1_i/vid_phy_controller_0/inst/gt_wrapper_inst/inst/gen_gtwizard_gthe4_top.design_1_vid_phy_controller_0_0_gtwrapper_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_cpll_cal_gthe4.gen_cpll_cal_inst[0].gtwizard_ultrascale_v1_7_4_gthe4_cpll_cal_inst/gtwizard_ultrascale_v1_7_4_gthe4_cpll_cal_rx_i/gen_cal_rx_en.bufg_gt_rxoutclkmon_inst (BUFG_GT.CE) is provisionally placed by clockplacer on BUFG_GT_X0Y1

Clock Rule: rule_bufgsync_bufg_withGTDriver
Status: PASS
Rule Description: A BUFG_GT_SYNC driving a BUFG_GT must be placed in the same clock region of the device
as the BUFG_GT
design_1_i/vid_phy_controller_0/inst/gt_wrapper_inst/inst/gen_gtwizard_gthe4_top.design_1_vid_phy_controller_0_0_gtwrapper_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/BUFG_GT_SYNC (BUFG_GT_SYNC.CESYNC) is provisionally placed by clockplacer on BUFG_GT_SYNC_X0Y1
design_1_i/vid_phy_controller_0/inst/gt_wrapper_inst/inst/gen_gtwizard_gthe4_top.design_1_vid_phy_controller_0_0_gtwrapper_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_cpll_cal_gthe4.gen_cpll_cal_inst[0].gtwizard_ultrascale_v1_7_4_gthe4_cpll_cal_inst/gtwizard_ultrascale_v1_7_4_gthe4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst (BUFG_GT.CE) is provisionally placed by clockplacer on BUFG_GT_X0Y2
design_1_i/vid_phy_controller_0/inst/gt_usrclk_source_inst/tx_mmcm.bufg_gt_tx_usrclk_inst (BUFG_GT.CE) is provisionally placed by clockplacer on BUFG_GT_X0Y0

Clock Rule: rule_bufgsync_bufg_withGTDriver
Status: PASS
Rule Description: A BUFG_GT_SYNC driving a BUFG_GT must be placed in the same clock region of the device
as the BUFG_GT
design_1_i/vid_phy_controller_0/inst/gt_wrapper_inst/inst/gen_gtwizard_gthe4_top.design_1_vid_phy_controller_0_0_gtwrapper_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/BUFG_GT_SYNC_2 (BUFG_GT_SYNC.CESYNC) is provisionally placed by clockplacer on BUFG_GT_SYNC_X0Y4
design_1_i/vid_phy_controller_0/inst/gt_wrapper_inst/inst/gen_gtwizard_gthe4_top.design_1_vid_phy_controller_0_0_gtwrapper_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_cpll_cal_gthe4.gen_cpll_cal_inst[1].gtwizard_ultrascale_v1_7_4_gthe4_cpll_cal_inst/gtwizard_ultrascale_v1_7_4_gthe4_cpll_cal_rx_i/gen_cal_rx_en.bufg_gt_rxoutclkmon_inst (BUFG_GT.CE) is provisionally placed by clockplacer on BUFG_GT_X0Y3

Clock Rule: rule_bufgsync_bufg_withGTDriver
Status: PASS
Rule Description: A BUFG_GT_SYNC driving a BUFG_GT must be placed in the same clock region of the device
as the BUFG_GT
design_1_i/vid_phy_controller_0/inst/gt_wrapper_inst/inst/gen_gtwizard_gthe4_top.design_1_vid_phy_controller_0_0_gtwrapper_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/BUFG_GT_SYNC_3 (BUFG_GT_SYNC.CESYNC) is provisionally placed by clockplacer on BUFG_GT_SYNC_X0Y2
design_1_i/vid_phy_controller_0/inst/gt_wrapper_inst/inst/gen_gtwizard_gthe4_top.design_1_vid_phy_controller_0_0_gtwrapper_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_cpll_cal_gthe4.gen_cpll_cal_inst[1].gtwizard_ultrascale_v1_7_4_gthe4_cpll_cal_inst/gtwizard_ultrascale_v1_7_4_gthe4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst (BUFG_GT.CE) is provisionally placed by clockplacer on BUFG_GT_X0Y4

Clock Rule: rule_bufgsync_bufg_withGTDriver
Status: PASS
Rule Description: A BUFG_GT_SYNC driving a BUFG_GT must be placed in the same clock region of the device
as the BUFG_GT
design_1_i/vid_phy_controller_0/inst/gt_wrapper_inst/inst/gen_gtwizard_gthe4_top.design_1_vid_phy_controller_0_0_gtwrapper_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/BUFG_GT_SYNC_4 (BUFG_GT_SYNC.CESYNC) is provisionally placed by clockplacer on BUFG_GT_SYNC_X0Y10
design_1_i/vid_phy_controller_0/inst/gt_wrapper_inst/inst/gen_gtwizard_gthe4_top.design_1_vid_phy_controller_0_0_gtwrapper_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_cpll_cal_gthe4.gen_cpll_cal_inst[2].gtwizard_ultrascale_v1_7_4_gthe4_cpll_cal_inst/gtwizard_ultrascale_v1_7_4_gthe4_cpll_cal_rx_i/gen_cal_rx_en.bufg_gt_rxoutclkmon_inst (BUFG_GT.CE) is provisionally placed by clockplacer on BUFG_GT_X0Y5

Clock Rule: rule_bufgsync_bufg_withGTDriver
Status: PASS
Rule Description: A BUFG_GT_SYNC driving a BUFG_GT must be placed in the same clock region of the device
as the BUFG_GT
design_1_i/vid_phy_controller_0/inst/gt_wrapper_inst/inst/gen_gtwizard_gthe4_top.design_1_vid_phy_controller_0_0_gtwrapper_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/BUFG_GT_SYNC_5 (BUFG_GT_SYNC.CESYNC) is provisionally placed by clockplacer on BUFG_GT_SYNC_X0Y8
and design_1_i/vid_phy_controller_0/inst/gt_wrapper_inst/inst/gen_gtwizard_gthe4_top.design_1_vid_phy_controller_0_0_gtwrapper_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_cpll_cal_gthe4.gen_cpll_cal_inst[2].gtwizard_ultrascale_v1_7_4_gthe4_cpll_cal_inst/gtwizard_ultrascale_v1_7_4_gthe4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst (BUFG_GT.CE) is provisionally placed by clockplacer on BUFG_GT_X0Y6

 

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Adventurer
Adventurer
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Registered: ‎10-18-2017

Re: Zynq UltraScale+: [Place 30-99] Placer failed with error: 'IO Clock Placer failed'

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Thanks, just as a heads up, I was able to get implementation to complete by adding the suggested timing constraint for the failed timing rule:

set_property CLOCK_DEDICATED_ROUTE ANY_CMT_COLUMN [get_nets design_1_i/vid_phy_controller_0/inst/gt_usrclk_source_inst/gtrefclk1_in[0]]
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Scholar xilinxacct
Scholar
342 Views
Registered: ‎10-23-2018

Re: Zynq UltraScale+: [Place 30-99] Placer failed with error: 'IO Clock Placer failed'

Jump to solution
0 Kudos
Adventurer
Adventurer
339 Views
Registered: ‎10-18-2017

Re: Zynq UltraScale+: [Place 30-99] Placer failed with error: 'IO Clock Placer failed'

Jump to solution
Thanks, just as a heads up, I was able to get implementation to complete by adding the suggested timing constraint for the failed timing rule:

set_property CLOCK_DEDICATED_ROUTE ANY_CMT_COLUMN [get_nets design_1_i/vid_phy_controller_0/inst/gt_usrclk_source_inst/gtrefclk1_in[0]]