UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Highlighted
Adventurer
Adventurer
177 Views
Registered: ‎07-27-2010

adding new output to project

Hi 

I have a code that runs perfectly but when I add some test signal and assign the pins it give the following error 

ERROR: Drc 23-20] Rule violation (UCIO-1) Unconstrained Logical Port - 1 out of 92 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined. To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: test_LA[15]

 

I have defined constraints for all the pins

Please suggest some solution

Regards

uzmeed

4 Replies
Xilinx Employee
Xilinx Employee
173 Views
Registered: ‎05-22-2018

Re: adding new output to project

Hi @uzmeed ,

Please check this AR# link, might be helpful:

https://www.xilinx.com/support/answers/56354.html

Thanks,

Raj

0 Kudos
Moderator
Moderator
157 Views
Registered: ‎11-04-2010

Re: adding new output to project

Hi, @uzmeed ,

You can check in the implemented design to see whether the port "test_LA[15]" is placed in the expected loc? 

If the port "test_LA[15]" is placed in expected loc, you can use the rshekhaw's method to suppress the error message.

If the port "test_LA[15]" is not placed in expected loc, please check when the user's package_pin property are missing. (You can open the opt.dcp, place.dcp and routed.dcp one by one to confirm)

-------------------------------------------------------------------------
Don't forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------
0 Kudos
Adventurer
Adventurer
118 Views
Registered: ‎07-27-2010

Re: adding new output to project

Hi @hongh 

I assigned a different pin to the signal and bitsteam generated sucessfully.

I am a bit confused in using the method mentioned by @rshekhaw  as it states that using this option will demage the FPGA, does it really happens that a wrong assignment may cause the FPGA a permanent damage.

 

Regards

Uzmeed

0 Kudos
Xilinx Employee
Xilinx Employee
112 Views
Registered: ‎05-22-2018

Re: adding new output to project

Hi @uzmeed ,

Although Vivado allows you to disable and downgrade the severity of the built-in DRC
Objects, this practice is highly discouraged as it can cause unpredictable results and could potentially
cause permanent damage to the device.

Thanks,

Raj

0 Kudos