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Explorer
Explorer
15,084 Views
Registered: ‎11-23-2013

can't set property VREF

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In my .xdc file, I write "set_property VREF {Y18 AE16 AD3 W4} [current_design]" to set the VREF pins for my DDR3 DIMM interface.

 

But after the implementation, Vivado give a critical warning that said

[Netlist 29-69] Cannot set property 'VREF', because the property does not exist for objects of type 'design'. ["E:/YCYK/FPGA/K7_325_DDR3_X14/TEST/TEST.srcs/constrs_1/imports/new/top.xdc":449]

 

Why does the message mean?

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Xilinx Employee
Xilinx Employee
16,892 Views
Registered: ‎01-03-2008

Re: can't set property VREF

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After a bit of checking I confirmed that VREF was an attribute that was only supported for some CPLD families and never applied to FPGAs.  The inclusion in some of the Vivado documentation, UG903 and UG911, is a mistake and the references will be removed.

 

Remove the constraint from XDC.

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Xilinx Employee
Xilinx Employee
15,081 Views
Registered: ‎07-11-2011

Re: can't set property VREF

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Hi,

 

Also are you trying to set internal vref for specific DDR3 pins without enabling internal vref option in the GUI?

If you are using MIG for your DDR3 DIMM I think IP will generate appropriate constraints based on your GUI settings.

Have you checked with it and wanted to edit xdc for any reason, can you share more inputs like which device, tool version etc?

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Explorer
Explorer
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Registered: ‎11-23-2013

Re: can't set property VREF

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The internal vref can be used only when the DDR3 working below 800Mb/s. So I used external VREF.

The device I used is Kintex7 325, -2 speed
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Explorer
Explorer
15,065 Views
Registered: ‎11-23-2013

Re: can't set property VREF

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The ug911 gives an example of migrating CONFIG VREF to vivado. The example is:

 

set_property VREF {E11 F11} [current_design]

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Explorer
Explorer
15,064 Views
Registered: ‎11-23-2013

Re: can't set property VREF

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I tried this, but the vivado give the warning above

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Explorer
Explorer
15,059 Views
Registered: ‎11-23-2013

Re: can't set property VREF

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Tool version is Vivado 2013.2
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Explorer
Explorer
15,054 Views
Registered: ‎11-23-2013

Re: can't set property VREF

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I am sorry the topic is a little confused.

 

I met that critical warning when I tried to set the VREF pin for DDR3 banks, not to set the VREF voltage.

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Xilinx Employee
Xilinx Employee
15,031 Views
Registered: ‎07-11-2011

Re: can't set property VREF

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Got it, but I am not sure if you really want to specify that constraint in xdc for MIG based designs as the vref pins for specific byte groups(Inputs only- DQ) are fixed and are known to MIG named something like T0, 1, 2_vref....

 

What is your device package and DDR3 DQ interface width and placed in which banks?

Have you gone through the pinout list .txt from UG475 and verified Y18 AE16 AD3 W4 are all vref pins for your selected package ?

 

Is it MIG example design or custom design?

 

Edit:- I also remember in on of your IO.rpt files you will see the text vref rquired for vref pins in the banks where MIG  is placed.

Please implemnet the design with default pinout given by MIG for your settings and check if the tool is detecting the vref pins for your DIMM

 

Hope this helps

 

Regards,

Vanitha

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Explorer
Explorer
15,007 Views
Registered: ‎11-23-2013

Re: can't set property VREF

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Things become wired. I tried the example design which can be used for DDR3 SODIMM, and add the VREF pins constrains in the .xdc file. The Vivado gives the same critical warning. Data width is 64.

 

The device I used is xc7k325tffg676-2, and I checked the pinout file. Y18 AE16 AD3 and W4 are the VREF pins for Bank 32 and 34. I allocated all DQ, DQS and DM pins in the two banks. All the control and address pins allocated in Bank 33.

 

My pin assignment was based on the example design, and just exchanged some pins. The exchangement complied with the rules. Both the example design and the custom design give the same critical warning if I add the VREF pins constrains in the .xdc file.

 

The .xdc file from the example design doesn't constrain the VREF pins. I think users should add the VREF pins into their design in order to make the Vivado verify the assignments. That is the correct and safe way. But the Vivado doesn't consider it as valid for object "design".

 

This maybe a bug of Vivado 2013.2. I do not have a new version of Vivado. Someone may try it in a new version.

 

 

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Xilinx Employee
Xilinx Employee
14,983 Views
Registered: ‎07-11-2011

Re: can't set property VREF

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Hi,

 

I got what you are saying but from MIG perspective you do not need that constraint.

If you worry the rest of your design might occupy those pins you can try to use prohibit constarint

But I think there should not be any reason why Vivado gives critical warning when the vref pins are same as MIG expected.

I will try replicate it at my end and will file CR.

 

Thanks for bringing this to our attention

 

 

Regards,

Vanitha

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Explorer
Explorer
9,153 Views
Registered: ‎11-23-2013

Re: can't set property VREF

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Hi,

vsrunga, thanks a lot.

 

I will describe my question as detailed as possible next time.

If there is any conclusion about this problem, please reply me, thank you!

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Xilinx Employee
Xilinx Employee
9,147 Views
Registered: ‎01-03-2008

Re: can't set property VREF

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The allocation of VREF pins of the device are handled automatically by the software. 

 

Where did you read that you need to add the "set_property VREF {Y18 AE16 AD3 W4} [current_design]"constraint to your design?

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Xilinx Employee
Xilinx Employee
16,893 Views
Registered: ‎01-03-2008

Re: can't set property VREF

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After a bit of checking I confirmed that VREF was an attribute that was only supported for some CPLD families and never applied to FPGAs.  The inclusion in some of the Vivado documentation, UG903 and UG911, is a mistake and the references will be removed.

 

Remove the constraint from XDC.

------Have you tried typing your question into Google? If not you should before posting.
Too many results? Try adding site:www.xilinx.com
0 Kudos
Explorer
Explorer
9,138 Views
Registered: ‎11-23-2013

Re: can't set property VREF

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Thank you!

 

I will remove that constrain.

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2,334 Views
Registered: ‎03-12-2015

Re: can't set property VREF

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Can we use Vref pin as IO (inout signal)?

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