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Registered: ‎08-23-2020

connecting spi clock and setup its constrains


I want to use spi to send data to my board(so spi interface of my board is slave). I wrote some constraints for spi interface which is in the following order:

set_property PACKAGE_PIN L14 [get_ports {CSn}]
set_property PACKAGE_PIN L15 [get_ports {SCLK}]
set_property PACKAGE_PIN K16 [get_ports {MISO}]
set_property PACKAGE_PIN J16 [get_ports {MOSI}]

set_property IOSTANDARD LVCMOS33 [get_ports {CSn}]
set_property IOSTANDARD LVCMOS33 [get_ports {SCLK}]
set_property IOSTANDARD LVCMOS33 [get_ports {MISO}]
set_property IOSTANDARD LVCMOS33 [get_ports {MOSI}]

I used 2 asynchronous AXI4-Stream Data FIFO, one for receive and one for send and they are connected to a DMA. besides i'm using a custom ipcore for converting spi protocol to axi4-stream. one of clock input pins of my FIFOs is connected to SCLK which is an external interface and another clock input is connected to FCLK pin of my ZYNQ(which is internal). Also SCLK is connected to my custom ipcore. Also my board is zturn7020.

My design is validated without any error and critical warning. Also synthesis is done successfully; how ever in the implementation section I have the following errors:

[Place 30-574] Poor placement for routing between an IO pin and BUFG. If this sub optimal condition is acceptable for this design, you may use the CLOCK_DEDICATED_ROUTE constraint in the .xdc file to demote this message to a WARNING. However, the use of this override is highly discouraged. These examples can be used directly in the .xdc file to override this clock rule.
	< set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets SCLK_IBUF] >

	SCLK_IBUF_inst (IBUF.O) is locked to IOB_X1Y105
	 and SCLK_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y31

[Place 30-99] Placer failed with error: 'IO Clock Placer failed'
Please review all ERROR, CRITICAL WARNING, and WARNING messages during placement to understand the cause for failure.

[Common 17-69] Command failed: Placer could not place all instances

I think the problem is related to my constraints but I don't know what should i do .


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Xilinx Employee
Xilinx Employee
Registered: ‎01-30-2019

Hi @SepehrMSP 

Can you try the following and let us know.

Open Synthesized design, select the IOB in device view and check its Clock Region.

after this put the following constraint in your xdc

set_property CLOCK_REGION <> [get_cells <BUFG cell name after synthesis>]

and then go for implementation. 




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