07-13-2019 06:07 AM - edited 07-14-2019 05:25 AM
i am trying to implement an for matrix multiplication (4x4 multiplied by 4x4 matrix),where inputs are given from the sdk. each input 8 bits.
The problem is i am not getting the values which have changing values.what ever value at the done signal is getting at the output. Also if i give some constant value at the temporary variables a1,a2,b1,b2,etc output is getting correctly.But not when assiging values from slv_reg.
i am also attaching the file containing the code.
can anyone please help me with this.
07-14-2019 05:29 AM
sorry i thought i added the code file previously but it didn't get uploaded. now i have attached the code file. The use logic is towards the end of the code.
07-14-2019 07:30 AM
Okay, yeah, let's see ...
Just my two cents,
07-14-2019 09:22 AM
First of all,Thank you so much for replying .
Actually i am a beginer ,so what you are telling about AXI i didn't get that much.
what i want is work that state machine correctly. i have simulated the state machine separately and it works also, but when i tried to create an ip using it it doesn't work.
In the custom ip if i am giving some fixed values to a1,a2,a3,a4,b1,b2,b3,b4 , i am correctly getting the cout.
example: a1=8'h01, a2=8'h02, a3=8'h03 etc
But if i am giving a1=slv_reg0[31:24] then zero is getting at the output.
with this i am attaching the code for state machine i have simulated.also attaching the sdk code.
07-14-2019 01:59 PM
Perhaps this might help: Notice how two AXI read requests generate only a single read response. That's called a bug.
Sadly, given that this is a bug in the Vivado generated portion of your code ... it's a pretty common mistake. (Any Xillinx employees listening? @demarco perhaps?)
I might offer to spend some more time with your code, but you have some other bugs you need to fix first. For example ...
I've also noticed, going through your code, that you are thinking of things that will happen one at a time. Try to think instead of how everything will happen at once, and then use that to your advantage. An example of that would be the multiplication implementation shown above. Consider setting as few variables as possible in an always block, and only merge variables together when the if-then-case structure is (nearly) identical.
One final thing: Verilog is an easy language to make a mistake in. Consider 1) Adding the line `default_nettype none // to the top of your Verilog file, and 2) running "verilator -Wall -cc matrixp.v" on your file. That'll run a lint pass to highlight bugs for you. It won't necessarily find all of them, but it will find many of them and its a lot faster to run than Vivado Synthesis is. These two steps will save you from a multitude of troubles further on.
Oh, and ... No, I still haven't pointed out the problem you are having with your state machine. Try fixing these problems first, and then you'll have a better chance of being right later.
For more information, consider my beginner's tutorial. I think you might learn a lot from it, especially in the way of how to debug your code.
Hope that helps,