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hamze
Adventurer
Adventurer
10,047 Views
Registered: ‎11-09-2010

external maping tool

Hello,

I am engaged in a university project to implement some EDA algorithms, like mapping or routing (not synthesis). My Question is does the xilinx ISE ( or even vivado ) give the output of each phase like synthesis or placement in a user readable format? then we could replace some part of it with our own tools? to check how well is our algroithms in comparision with Xilinx?

thanks

 

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aher
Xilinx Employee
Xilinx Employee
10,043 Views
Registered: ‎07-21-2014

Hi,

you can read log files generated during synthesis/implementation process. in case of vivado you can find it in
Project_location\project_1\project_1.runs\synth_1
folder or
impl_1 folder in case of implementation.

in ISE as well you can find all the log files of each stage in project folder.

-Shreyas
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vijayak
Xilinx Employee
Xilinx Employee
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Registered: ‎10-24-2013

Hi @hamze

 

In vivado GUI, to the bottom side there is a section called reports (refer to the screenshot attached.

 

That section will show the report files of each phase of vivado design flow.

Thanks,Vijay
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hamze
Adventurer
Adventurer
10,024 Views
Registered: ‎11-09-2010

May I didn't explain correctly. I mean is there any readable text file for user, showing the netlist after sysnthesis? inside report there is just some statistics about utilizatin of different resources.
Actually in ISE output of synthesize was .ngr ( or .ngc ) file , but unfortunately it was not readable in text format. It could only be viewed graphically when you open it by ISE (RTL view).
As I explained before, I wanted to implement my own simple placement algorithm, then I need readable syntesize output in text format.....

Generally is such thing poosible?  Firstly I guess Xilinx doesn't exibit its intermediate outputs to user... only final bit stream is given to usre....

Thanks

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bwade
Scholar
Scholar
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Registered: ‎07-01-2008

The ISE tools contain a commandline utility that can be used to convert an NCD file to text and back:

 

xdl -ncd2xdl xxx.ncd xxx.xdl

xdl -xdl2ncd xxx.xdl xxx.ncd

 

The post-map NCD will have placement information. The post-par NCD wil have placement and routing information. The .xdl text file is in a netlist format.

 

Bret

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hamze
Adventurer
Adventurer
10,006 Views
Registered: ‎11-09-2010

thanks you again.
beside those, as I checked, the simulation model of mapping, and place&route are also what I want. earlier my input, later my output.

and final question :

in HDL simulation model of place&route, placement information is provided ( which slices or I/O pads are used exactly ).

but what about internal routing among slices? how can I know exactly which routing recourses are used? fpga wires are also addressable? ( for simplicity I only assumed my design is a combinational logic).

thanks

 

 

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bwade
Scholar
Scholar
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Registered: ‎07-01-2008

Each slice has a configuration string that defines the internal connectivity. There are what I call "configuration muxes" that define the internal connectivity and you will be able to see how they are configured in the config string. To understand this better, I suggest that you examine a design in FPGA Editor and for various slice components cross reference the graphical representation in the Logic Block Editor against the config strings.

 

Bret

hamze
Adventurer
Adventurer
9,484 Views
Registered: ‎11-09-2010

Thanks bret,

I already checked the FPGA place and routing output in graphical view, but I need to see it and then read it in text format. Briefly:

  1. How can I see the output of routing in a text file? I know that there are some switching box inside FPGA, how can I know what is the internal configuration of each switch box for special routing?
  2. is there any special document that describes the detailed internal structure and routing resources of Xilinx FPGA? I know each FPGA has its own sttructure, suppose for Spartan 3E I want to implement my own routing algorithm for an already "placed" design" and then compare it with xilinx routing.

I should also mentione that I read the outptu of placement inside this folder: project\netgen\par\mytop_timesim.v
thanks

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