10-14-2015 03:04 AM
I am engaged in a university project to implement some EDA algorithms, like mapping or routing (not synthesis). My Question is does the xilinx ISE ( or even vivado ) give the output of each phase like synthesis or placement in a user readable format? then we could replace some part of it with our own tools? to check how well is our algroithms in comparision with Xilinx?
10-14-2015 03:10 AM
10-14-2015 04:45 AM
In vivado GUI, to the bottom side there is a section called reports (refer to the screenshot attached.
That section will show the report files of each phase of vivado design flow.
10-14-2015 11:43 AM - edited 10-14-2015 11:50 AM
May I didn't explain correctly. I mean is there any readable text file for user, showing the netlist after sysnthesis? inside report there is just some statistics about utilizatin of different resources.
Actually in ISE output of synthesize was .ngr ( or .ngc ) file , but unfortunately it was not readable in text format. It could only be viewed graphically when you open it by ISE (RTL view).
As I explained before, I wanted to implement my own simple placement algorithm, then I need readable syntesize output in text format.....
Generally is such thing poosible? Firstly I guess Xilinx doesn't exibit its intermediate outputs to user... only final bit stream is given to usre....
10-14-2015 12:21 PM
The ISE tools contain a commandline utility that can be used to convert an NCD file to text and back:
xdl -ncd2xdl xxx.ncd xxx.xdl
xdl -xdl2ncd xxx.xdl xxx.ncd
The post-map NCD will have placement information. The post-par NCD wil have placement and routing information. The .xdl text file is in a netlist format.
10-15-2015 01:13 AM
thanks you again.
beside those, as I checked, the simulation model of mapping, and place&route are also what I want. earlier my input, later my output.
and final question :
in HDL simulation model of place&route, placement information is provided ( which slices or I/O pads are used exactly ).
but what about internal routing among slices? how can I know exactly which routing recourses are used? fpga wires are also addressable? ( for simplicity I only assumed my design is a combinational logic).
10-15-2015 09:33 AM
Each slice has a configuration string that defines the internal connectivity. There are what I call "configuration muxes" that define the internal connectivity and you will be able to see how they are configured in the config string. To understand this better, I suggest that you examine a design in FPGA Editor and for various slice components cross reference the graphical representation in the Logic Block Editor against the config strings.
12-15-2015 08:12 AM - edited 12-15-2015 08:16 AM
I already checked the FPGA place and routing output in graphical view, but I need to see it and then read it in text format. Briefly:
I should also mentione that I read the outptu of placement inside this folder: project\netgen\par\mytop_timesim.v