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snchao
Newbie
Newbie
1,747 Views
Registered: ‎09-06-2017

how to fixed [Vivado 12-2285] Cannot set LOC property of instance ?

 

Dear Sir,

I am using Vivado v2017.1 for MIG IP DDR3.

My device part is  xcvu440-flga2892-1-c.

Here is critical warning log, how to fixed it ?

 

 

CRITICAL WARNING: [Vivado 12-2285] Cannot set LOC property of instance 'u_pd_main/u_core_top/u_ddr_top/u_mig/inst/u_ddr3_mem_intfc/u_mig_ddr3_phy/inst/u_ddr_iob/genByte[1].u_ddr_iob_byte/genBuf[0].genblk1.OBUF', Instance u_pd_main/u_core_top/u_ddr_top/u_mig/inst/u_ddr3_mem_intfc/u_mig_ddr3_phy/inst/u_ddr_iob/genByte[1].u_ddr_iob_byte/genBuf[0].genblk1.OBUF can not be placed in OUTBUF of site IOB_X0Y68 because the bel is occupied by u_pd_main/u_core_top/u_ddr_top/u_mig/inst/u_ddr3_mem_intfc/u_mig_ddr3_phy/inst/u_ddr_iob/genByte[5].u_ddr_iob_byte/genBuf[3].genblk1.OBUF(port:c0_ddr3_addr[8]). This could be caused by bel constraint conflict [/projusers/t0337af8/ZIV/UT0337A/UT0337A/0808_ASUS/ASUS_with_NEW_diff_DDR/FPGA/arc_ddr_no_pisp/db_arc_ddr_no_pisp_vivado_run/pad_top_edif.xdc:2616]
Resolution: When using BEL constraints, ensure the BEL constraints are defined before the LOC constraints to avoid conflicts at a given site.

 

thanks

~SN

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vemulad
Xilinx Employee
Xilinx Employee
1,714 Views
Registered: ‎09-20-2012

Hi @snchao

 

Are you using Vivado GUI or scripts to run synthesis and implementation?

 

Did you assign the locations to MIG pins on elaborated or synthesized design and run report_drc to ensure pinout is valid?

 

You will need to rerun implementation from opt_design stage when you change the MIG pinout.

Thanks,
Deepika.
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