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Newbie
Newbie
5,255 Views
Registered: ‎02-17-2009

how to keep an LVDS input from being removed so i can have the termination resistor

I've a design with a number of LVDS inputs defined, but not all used.  There are different bit files loaded for specific applications and not all my applications use all the LVDS inputs defined.  For a given implementation the unused inputs are optimized out, which is fine.

 

But now i want one of the inputs to stay just to provide the LVDS termination resistor, and i can't find how to keep it.  KEEP seems to to just keep nets from being collapsed away in logic optimization and doesn't seem to help if the logic around the net is optimized away completely.

 

I'd wire that input to some output pin just to keep it except I am full up on io.

 

From my top level Verilog:

 

IBUFDS #(.DIFF_TERM("TRUE"),.IOSTANDARD("LVDS_25"))  IBUFDS_inst00(.I(D0_p_pin) , .IB(D0_n_pin) , .O(IntDx00));
IBUFDS #(.DIFF_TERM("TRUE"),.IOSTANDARD("LVDS_25"))  IBUFDS_inst01(.I(D1_p_pin) , .IB(D1_n_pin) , .O(IntDx01));
IBUFDS #(.DIFF_TERM("TRUE"),.IOSTANDARD("LVDS_25"))  IBUFDS_inst02(.I(D2_p_pin) , .IB(D2_n_pin) , .O(IntDx02));
IBUFDS #(.DIFF_TERM("TRUE"),.IOSTANDARD("LVDS_25"))  IBUFDS_inst03(.I(D3_p_pin) , .IB(D3_n_pin) , .O(IntDx03));
IBUFDS #(.DIFF_TERM("TRUE"),.IOSTANDARD("LVDS_25"))  IBUFDS_inst04(.I(D4_p_pin) , .IB(D4_n_pin) , .O(IntDx04));
etc

 

and from my ucf:

 

NET "D0_p_pin" LOC = "A16" | IOSTANDARD = "LVDS_25";

NET "D0_n_pin" LOC = "B16" | IOSTANDARD = "LVDS_25";

NET "D1_p_pin" LOC = "B15" | IOSTANDARD = "LVDS_25";

NET "D1_n_pin" LOC = "A15" | IOSTANDARD = "LVDS_25";

NET "D2_p_pin" LOC = "C15" | IOSTANDARD = "LVDS_25";

NET "D2_n_pin" LOC = "C16" | IOSTANDARD = "LVDS_25";

NET "D3_p_pin" LOC = "G16" | IOSTANDARD = "LVDS_25";

NET "D3_n_pin" LOC = "G17" | IOSTANDARD = "LVDS_25";

NET "D4_p_pin" LOC = "D19" | IOSTANDARD = "LVDS_25";

NET "D4_n_pin" LOC = "E19" | IOSTANDARD = "LVDS_25";

 etc

 

and later in the ucf:

# Differential termination resistors in the FPGA

INST "IBUFDS_inst00" DIFF_TERM = TRUE;

INST "IBUFDS_inst01" DIFF_TERM = TRUE;

INST "IBUFDS_inst02" DIFF_TERM = TRUE;

INST "IBUFDS_inst03" DIFF_TERM = TRUE;

INST "IBUFDS_inst04" DIFF_TERM = TRUE;

etc

INST "IBUFDS_inst00" IOSTANDARD="LVDS_25";

INST "IBUFDS_inst01" IOSTANDARD="LVDS_25";

INST "IBUFDS_inst02" IOSTANDARD="LVDS_25";

INST "IBUFDS_inst03" IOSTANDARD="LVDS_25";

INST "IBUFDS_inst04" IOSTANDARD="LVDS_25";

etc.

In this case my data begins with the lsb on data bit 3 and my internal logic processes the data from inputs 3 and up, so inputs 0, 1, 2 get removed.  I need to keep at least input 2.

 

I have to think this is a very common or basic question, but i can't find the solution searching around the Xilinx site.  I'm using a Virtex4, BTW and Project Navigator 9.2.02i.

 

Thanks.

R Prentice

 

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1 Reply
Historian
Historian
5,244 Views
Registered: ‎02-25-2008

Re: how to keep an LVDS input from being removed so i can have the termination resistor

The simplest way to ensure the tools don't optimize anything away is to create an output pin called something like PreventOpt. Instantiate all of the LVDS input buffers you need. Then simply AND the outputs of all of those LVDS input buffers, and drive the PreventOpt output pin with the output of that big AND gate. Sure, it wastes a pin and some LUTs, but it's the simplest solution I found. There might be constraint options and such, but this way is the easiest.

 

-a

----------------------------Yes, I do this for a living.
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