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saradstha
Visitor
Visitor
9,102 Views
Registered: ‎10-15-2013

iobuf implementation

Hi All!

 I want to use bidrectional data bus of 32 bits in spartan 6 (lx25) (tool use : ISE 14.1). For this , I have used following code. FPGA is slave device here.

***code snippet**

library unisim;
use unisim.vcomponents.all;

component IOBUF is
  generic(
      CAPACITANCE                : string     := "DONT_CARE";
      DRIVE                               : integer     := 12;
      IBUF_DELAY_VALUE     : string := "0";
      IBUF_LOW_PWR           : boolean    :=  TRUE;
      IFD_DELAY_VALUE       : string := "AUTO";
      IOSTANDARD                : string       := "DEFAULT";
      SLEW                             : string       := "SLOW"
    );
  port(
    O  : out   std_ulogic;
    IO : inout std_ulogic;
    I  : in    std_ulogic;
    T  : in    std_ulogic
  );
  end component;

********************************************

 

Problem: In chipscope, the bus holds some garbage value rather than the value master drives(writing to FPGA).

a)  Is it bus contention?

b) Do I  have to change  the attributes according the master device's IO specification (like drive current, voltage, capacitance,slew etc)?

c) Do I need to give constriants for pull up/ pull down for data bus?

Note :  The bus is holding  value correctly during read operation by Master(PEX 8311) (i.e, when FPGA is driving the bus).

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6 Replies
brucey
Xilinx Employee
Xilinx Employee
9,095 Views
Registered: ‎03-24-2010

a)How do you connect Chipscope core to your input? Directly? Do you have OFFSET IN constraints applied?

It seems one timing issue.

For b) and c), the Spartan® Family FPGAs board is more suitable.

Regards,
brucey
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saradstha
Visitor
Visitor
9,081 Views
Registered: ‎10-15-2013

Thanks Brucey! 

To see the input, io bus is assigned to the signal in clock process.

 

****

elsif (rising_edge(master_cllk)) then

       data_bus_reg <= io_bus;

        ----

         -----

a) To see in chipscope, data_bus_reg is mapped. I have not used any "offset in" constraint. What kind of timing issue??

b) and c) spartan 6 is intergrated in custom board.

 

 

 

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gszakacs
Instructor
Instructor
9,060 Views
Registered: ‎08-14-2007

You asked if this might be bus contention.  What is going on with the T input to the BUFIO when you are receiving data into the FPGA?  T should be high to disable the output drive of the FPGA.  It should be easy enough to add the T signal to your ChipScope if it isn't already there.

-- Gabor
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brucey
Xilinx Employee
Xilinx Employee
9,056 Views
Registered: ‎03-24-2010

To sample io_bus by data_bus_reg correctly, the setup and hold time requirement of data_bus_reg must be met. To check the timing, tools need to know the phase relationship between io_bus and master_clk. Thus, OFFSET IN constraints is needed. You may refer to UG625.

For the board, sorry that I mean the discussion board: Xilinx User Community Forums -> Xilinx Products -> Silicon Devices -> Spartan Family FPGAs.

Regards,
brucey
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saradstha
Visitor
Visitor
9,048 Views
Registered: ‎10-15-2013

Thanks !! T input to the IOBUF is high when  receiving data into the FPGA. That means it disabled output drive for FPGA. T signal is included in chipscope and is high during FPGA read.
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saradstha
Visitor
Visitor
9,044 Views
Registered: ‎10-15-2013

Thanks !
       FPGA is sampling  data bus and control signals (read/write, etc) according to master clk. So it is synchronous to the Master clock.  io_bus is synchronous to the master_clk and and data_bus_reg too. So, constraints may not be required.
 
 
Also, I will post the attribute related things on discussion board as per you mentioned. I just want to know whether attributes can affect the values on the data bus.
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