I am using ISE and I am using Verilog And I use Spartan6 SP605. I'd like to ask you, is there a way to prevent OBUF from being mapped automatically, even if the variable is declared OUTPUT when coding?What I want to do is to act as OUTPUT, but I don't want to do mapping and I want to see the results in P&R Simulation(about output).
look for verilog attributes
(*dont_touch = "true"*)(* KEEP = "TRUE" *)
for keeping registers from being removed from synthesis tool if their output doen't drive any module output