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Participant
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Registered: ‎11-21-2018

issue with set property in xdc

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i had used two differential clk inputs and it is differential , i need to generate the single ended output then i am using IBUFGDS as a template . But i didnt get the proper result , meanwhile i am facing issue in the bitstream generation as i.e., set property object.

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Moderator
Moderator
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Registered: ‎05-31-2017

@pallavi52 ,

Please check my last post, after making the mentioned modifications I was able to generate bitstream for test3.xpr project

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Xilinx Employee
Xilinx Employee
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Registered: ‎05-22-2018

Hi @pallavi52 ,

Can you please share what exactly the tool is throwing as error?

Thanks,

Raj

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Participant
Participant
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Registered: ‎11-21-2018
vivado 2018.3
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Xilinx Employee
Xilinx Employee
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Registered: ‎05-22-2018

Hi @pallavi52 ,

Please share the error message you are getting.

Thanks,

Raj

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Participant
Participant
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Registered: ‎11-21-2018
[runtcl-4] ERROR: [Common 17-55] 'set_property' expects at least one object. Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
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Xilinx Employee
Xilinx Employee
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Registered: ‎05-22-2018

Hi @pallavi52 ,

This error indicate that the object name specified in the constraint is not correct.

Please check this AR# link, might be helpful:

https://www.xilinx.com/support/answers/56169.html

Thanks,

Raj

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Participant
Participant
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Registered: ‎11-21-2018

Synthesis
[Netlist 29-177] Cannot set property 'IO_STANDARD' because the property does not exist. ["D:/Pallavi/newprojects/test1/test1.srcs/constrs_1/new/test1_xdc.xdc":21]

[Netlist 29-177] Cannot set property 'IO_STANDARD' because the property does not exist. ["D:/Pallavi/newprojects/test1/test1.srcs/constrs_1/new/test1_xdc.xdc":23]

[Netlist 29-177] Cannot set property 'IO_STANDARD' because the property does not exist. ["D:/Pallavi/newprojects/test1/test1.srcs/constrs_1/new/test1_xdc.xdc":27]

[Common 17-55] 'set_property' expects at least one object. ["D:/Pallavi/newprojects/test1/test1.srcs/constrs_1/new/test1_xdc.xdc":29]

Implementation
Design Initialization
[Netlist 29-177] Cannot set property 'IO_STANDARD' because the property does not exist. ["D:/Pallavi/newprojects/test1/test1.srcs/constrs_1/new/test1_xdc.xdc":21]

[Common 17-55] 'set_property' expects at least one object. ["D:/Pallavi/newprojects/test1/test1.srcs/constrs_1/new/test1_xdc.xdc":29]

Write Bitstream
[runtcl-4] ERROR: [Common 17-55] 'set_property' expects at least one object.
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
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Xilinx Employee
Xilinx Employee
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Registered: ‎05-22-2018

Hi @pallavi52 ,

I guess the issue is related to XDC Scoping Mechanism. How are you scoping out the object for setting IOSTANDARD, using get_ports or get_pins

Please check page no.69 for detailed information:

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2019_1/ug903-vivado-using-constraints.pdf

Hope the information will be helpful.

Thanks,

Raj

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Participant
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Registered: ‎11-21-2018
[runtcl-4] ERROR: [Common 17-55] 'set_property' expects at least one object.
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.

again i m facing the same issue, i had gone through the scoping concept, i didnt get more info about IOSTANDARD there. can you please help me with it.
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Moderator
Moderator
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Registered: ‎05-31-2017

HI @pallavi52 ,

Please share the XDC constraint which you are using on which the tool errors out with " 'set_property' expects at least one object".

You can also give a try in the vivado TCL console to check whether the command is able to fetch the pin/port/cell/net on which you are trying to set the property.

 

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Participant
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Registered: ‎11-21-2018
create_clock -name clk_out -period 10 [get_ports clk_out]
set_property CLOCK_DEDICATED_ROUTE TRUE [get_nets {clk_out_IBUFDS}];

set_property SCOPED_TO_REF diffclk [get_files test1_xdc.xdc]
set_property -dict { PACKAGE_PIN R5 IOSTANDARD LVDS25 } [get_ports { clk_n }];
set_property CLOCK_DEDICATED_ROUTE TRUE [get_nets {clk_n}];

set_property -dict { PACKAGE_PIN R6 IOSTANDARD LVDS25} [get_ports { clk_p }];
set_property CLOCK_DEDICATED_ROUTE TRUE [get_nets {clk_p}];

set_property -dict { PACKAGE_PIN AP29 IOSTANDARD LVCMOS33 } [get_ports {clk_out }];
set_property CLOCK_DEDICATED_ROUTE TRUE [get_nets {clk_out_IBUFDS}];
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i had checked the tcl console

[Fri Sep 13 11:55:37 2019] Launched impl_1...
Run output will be captured here: D:/P/newprojects/test1/test1.runs/impl_1/runme.log
reset_run synth_1
launch_runs impl_1 -to_step write_bitstream -jobs 2
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Xilinx Employee
Xilinx Employee
1,104 Views
Registered: ‎05-22-2018

Hi @pallavi52 ,

Can you please try to apply PACKAGE_PIN and IOSTANDARD property in seperately. For instance:

set_property -dict { PACKAGE_PIN R5 IOSTANDARD LVDS25 } [get_ports { clk_n }] aplly this as shown below:

#set_property PACKAGE_PIN R5 [get_ports clk_n]
and then at the bottom

set_property IOSTANDARD LVDS_25 [get_ports clk_n]

Thanks,

Raj

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Moderator
Moderator
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Registered: ‎03-16-2017

Hi @pallavi52 ,

Apply all your XDC (set_proeprty) commands in Vivado tcl console one by one after opening the synthesized design and observe carefully that what error tool throws after applying a set_property command. 

Make changes as will be shown in the errors and then again follow the same steps. And then save your design with new constraints. 

Regards,
hemangd

Don't forget to give kudos and mark it as accepted solution if your issue gets resolved.
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Xilinx Employee
Xilinx Employee
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Registered: ‎05-22-2018

Hi @pallavi52 ,

Did you issue got resolved?

Do you have further queries on this? If not, please mark the response that resolved your issue, as Accepted Solution and close the thread.

Thanks,

Raj

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Participant
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Registered: ‎11-21-2018
still i didnt get my issue solved , however the changes i do , i m getting the same issue..i.e., set property .....
[runtcl-4] ERROR: [Common 17-55] 'set_property' expects at least one object.
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.

Please help me with this issue
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Moderator
Moderator
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Registered: ‎03-16-2017

@pallavi52 

Share your testcase with XDC file to resolve this issue.

Regards,
hemangd

Don't forget to give kudos and mark it as accepted solution if your issue gets resolved.
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Participant
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Registered: ‎11-21-2018
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

library UNISIM;
use UNISIM.VComponents.all;

entity test1 is
Port ( clk_p : in STD_LOGIC;
clk_n : in STD_LOGIC;
clk_out : out STD_LOGIC);
end test1;

architecture Behavioral of test1 is

begin

IBUFDS_inst : IBUFDS
generic map (
DIFF_TERM => FALSE, -- Differential Termination
IBUF_LOW_PWR => TRUE, -- Low power (TRUE) vs. performance (FALSE) setting for referenced I/O standards
IOSTANDARD => "DEFAULT")
port map (
O => clk_out, -- Buffer output
I => clk_p, -- Diff_p buffer input (connect directly to top-level port)
IB => clk_n -- Diff_n buffer input (connect directly to top-level port)
);
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Participant
Participant
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Registered: ‎11-21-2018

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

library UNISIM;
use UNISIM.VComponents.all;

entity test1_tb is

end test1_tb;

architecture Behavioral of test1_tb is
component TEST1
Port ( clk_p : in STD_LOGIC;
clk_n : in STD_LOGIC;
clk_out : out STD_LOGIC);
end component;

signal clk_p : std_logic:= '0';
signal clk_n : std_logic:= '0';
-- signal clk_out : std_logic;

-- constant clk_period : time : = 10 ns;

begin

-- uut : TEST1 port map( clk_p => clk_p,
-- clk_n => clk_n,
-- clk_out => clk_out);
clk_process : process
begin

-- clk_p <= '0';
-- wait for 10 ns;

clk_p <= '1';
wait for 10 sec;

clk_p <= '0';
wait for 10 ns;

clk_n <= '0';
wait for 10 sec;

clk_n <= '1';
wait for 10 ns;

end process;

end Behavioral;
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Participant
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set_property IO_STANDARD LVDS_25 [get_ports {clk_p}]
set_property PACKAGE_PIN R6 [get_ports clk_p]
set_property IO_STANDARD LVDS_25 [get_ports {clk_n}]
set_property PACKAGE_PIN R5 [get_ports clk_n]

set_property PACKAGE_PIN AP29 [get_ports clk_out]
set_property IO_STANDARD LVCMOS33 [get_ports {clk_out}]
create_clock -name clk_out -period 10 [get_ports clk_out]
set_property CLOCK_DEDICATED_ROUTE TRUE [get_nets {clk_out_IBUFDS}];
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Xilinx Employee
Xilinx Employee
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Registered: ‎05-22-2018

Hi @pallavi52 ,

Remove the curly brackets for the set_property command as depicted and check whether it helps:

set_property IO_STANDARD LVDS_25 [get_ports {clk_p}] write it like this:


set_property IO_STANDARD LVDS_25 [get_ports clk_p]

Thanks,

Raj

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Participant
Participant
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Registered: ‎11-21-2018
no, i am getting the same issue
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Moderator
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Registered: ‎05-31-2017

HI @pallavi52 ,

Please try executing the command get_nets {clk_out_IBUFDS} command in vivado TCL console after opening the implementation schematic.

I am assuming the issue is with the below constraint as the tool might not be able to find the net because of which it is throwing the error.

set_property CLOCK_DEDICATED_ROUTE TRUE [get_nets {clk_out_IBUFDS}];

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Moderator
Moderator
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Registered: ‎05-08-2012

Hi @pallavi52 

The IOSTANDARD property does not have an underscore such as the below.

set_property IO_STANDARD LVCMOS33 [get_ports {clk_out}]

Can you change this to 

set_property IOSTANDARD LVCMOS33 [get_ports {clk_out}]

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2019_1/ug912-vivado-properties.pdf#page=251


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Xilinx Employee
Xilinx Employee
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Registered: ‎05-22-2018

Hi @pallavi52 ,

Did your issue got resolved?

If yes please mark the response that resolved your issue, as Accepted Solution and close the thread.

Thanks,

Raj

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Participant
Participant
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Registered: ‎11-21-2018
no, my issue didnt get solved.
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whatever the changes i did , the same issue i am facing . If it is possible , could u please transfer this issue to your superior .
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Moderator
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Registered: ‎01-16-2013

@pallavi52 

 

Can you share the archive project? From Vivado, select File-->Project-->Archive.. This will save your project in .zip file. Please share this .zip file.

From the snippet of xdc and RTL code shared, I dont think your design has net with name "clk_out_IBUFDS". You can open synthesized design and check this by running following command "get_nets {clk_out_IBUFDS}" to see if it returns a valid output. 

 

I will send you email from ezmove where you can upload the project archive and send it back to us. 

 

--Syed

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Did you check our new quick reference timing closure guide (UG1292)?
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Participant
Participant
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Registered: ‎11-21-2018
yes , i gone through the user manual ug192. i will send u mail. please check and resolve this issue
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Participant
Participant
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please go through the attachments

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