01-02-2014 04:29 PM
I keep getting the following error which stops the placement and wont route the design. I tried moving the MMCM to the correct half of the chip which moves the problem to another MMCM, BUFGCTRL pair. Is there a way to force the tool to chose MMCM/BUFGCTRL pairs that it can route to each other instead of me doing it manually for all my MMCMs since changing one, seems to break the others.
Place:1149 - Unroutable Placement! A MMCM / BUFGCTRL clock component pair have been found that are not placed at a routable MMCM / BUFGCTRL site pair. The MMCM component <system_top/axi_pcie_0/axi_pcie_0/comp_axi_enhanced_pcie/comp_enhanced_core_top_wrap/axi_pcie_enhanced_core_top_i/k7_pcie_7x_v1_4_inst/gt_ges.gt_top_i/pipe_wrapper_i/pipe_clock_int.pipe_clock_i/mmcm_i> is placed at site <MMCME2_ADV_X0Y0>. The corresponding BUFGCTRL component <system_top/axi_pcie_0/axi_pcie_0/comp_axi_enhanced_pcie/comp_enhanced_core_top_wrap/axi_pcie_enhanced_core_top_i/k7_pcie_7x_v1_4_inst/gt_ges.gt_top_i/pipe_wrapper_i/pipe_clock_int.pipe_clock_i/userclk2_i1.usrclk2_i1> is placed at site <BUFGCTRL_X0Y29>. The pair can use the fast path between the Clock Manager and the Clock buffer if the MMCM and...
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01-02-2014 08:07 PM - edited 01-02-2014 08:08 PM
Which version of ISE is this? Try using latest ISE 14.7.
How many MMCM and BUFG's are utilized in the design?
MMCMs in the top half of the device can only drive the BUFGs in the top half of the device and MMCMs in bottom half can only drive BUFGs in the bottom half. Similarly, onlyBUFGs in the same half of the device can be used as feedback to the MMCMs in the same half of the device.
You need to check whether the MMCM drives more than 16 BUFGs, which exceeds the number in half of the device. In this case, it's not possible for the tool to satisfy the clock placer rule.
In case the error is due to automatic placement failure, you can try manually locking the MMCM and BUFG down to the same half of device.
03-14-2014 10:48 AM
I met the same problem.
I'm using xps14.6.
The board im using is KC705 which fpga should has 32 BUFG. In my design, i only used 8 Bufgs.
Do you think if there are any other reasons for this problem?
And what i do is in XPS to do my own customized ip core. I don't find the place to launch fpga editor in XPS.
How can i manually locked the MMCM?
Thanks a lot.