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Contributor
Contributor
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Registered: ‎03-27-2017

opt_design ERROR Vivado 2018.3

I keep receiving the following error and am never able to complete the opt_design during Implementation.  Here is the Vivado Log:

opt_design completed successfully
opt_design: Time (s): cpu = 00:31:02 ; elapsed = 00:19:24 . Memory (MB): peak = 14150.246 ; gain = 7727.172
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.042 . Memory (MB): peak = 14150.246 ; gain = 0.000
INFO: [Timing 38-480] Writing timing data to binary archive.
Writing placer database...
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.069 . Memory (MB): peak = 14150.246 ; gain = 0.000
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.048 . Memory (MB): peak = 14150.246 ; gain = 0.000
Abnormal program termination (EXCEPTION_ACCESS_VIOLATION)
Please check 'D:/SNAPP/SNAPP_Rev31/SNAPP_Rev31.runs/impl_1/hs_err_pid20084.log' for details

 

 

hs_err_pid20084.log Contains:
#
# An unexpected error has occurred (EXCEPTION_ACCESS_VIOLATION)
#
Stack:
no stack trace available, please use hs_err_<pid>.dmp instead.

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2 Replies
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Contributor
Contributor
439 Views
Registered: ‎03-27-2017

Attached to this post is the full Implementation log

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Xilinx Employee
Xilinx Employee
389 Views
Registered: ‎01-30-2019

Hi @afgarrido ,

Are you using Vivado on windows? 

There was a similar issue reported previously, Can you try the following and let me know its outcomes so that I can confirm if your issue is the same.

1. Open Synthesized design - > Run opt_design - > write_checkpoint 

2. Open Synthesized design - > opt_design -> place_design -> write_checkpoint