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Observer
Observer
2,417 Views
Registered: ‎11-07-2017

place_design ERROR

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Hi,

 

I am following the attached Lab document from Xilinx. When I generate the bitstream, I am able to do the synthesis but while Implementation, it throws an error "place_design ERROR". I am attaching the screenshot of error and messages.

 

I followed the same lab document in the University PC, it was working back then but unfortunately not in my Laptop.

 

Thanks & regards

Vishav

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Moderator
Moderator
3,662 Views
Registered: ‎11-09-2015

Re: place_design ERROR

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Hi @vishav26,

 

This is unlikely to be a licensing issue. If it was you wouldn't have been able to run synthesis.

 

I think half of the issue could be solved by what @peadard pointed. You are not targeting the zybo for your project (so the step 2-1-5 might be missing and this is the one which configure the zynq IP).

 

Then did you renamed the external port GPIO_0 to btn? Could you share a screenshot of your BD?

 

Regards,

 

Florent


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Xilinx Employee
Xilinx Employee
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Registered: ‎08-01-2008

Re: place_design ERROR

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read the synthesis report . It seems resource over utilization in your design . Synthesis report must tell you are using >100 % resources available in target device. You may define some of the port as internal signals . The output which are not using outside can eb define as internal signals
Thanks and Regards
Balkrishan
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Moderator
Moderator
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Registered: ‎02-07-2008

Re: place_design ERROR

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@vishav26, I ran through the lab in question and did not encounter any issues (see attached implementation log file). I did this with 2017.3, can you try using this version as opposed to 2015.3?

 

A couple of things to check:

1) targeting the Zybo board and not just the device

2) ensure you've deselected all required peripherals as outlined in steps 2-2-3, 2-2-4 and 2-3-1.

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Observer
Observer
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Registered: ‎11-07-2017

Re: place_design ERROR

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I ran it first in 2017.3 and encountered the same issue. The system in my university Lab had 2015.3 version and I thought it can be version compatibility issues. Hence I downloaded 2015.3 but unfortunately I get this error.

I find this error only in my system as I ran it on my friend's PC and it works.

 

Can this error be linked to license as I am not sure which license I selected while downloading the Vivado?

 

Thanks & Regards

Vishav

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Moderator
Moderator
3,663 Views
Registered: ‎11-09-2015

Re: place_design ERROR

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Hi @vishav26,

 

This is unlikely to be a licensing issue. If it was you wouldn't have been able to run synthesis.

 

I think half of the issue could be solved by what @peadard pointed. You are not targeting the zybo for your project (so the step 2-1-5 might be missing and this is the one which configure the zynq IP).

 

Then did you renamed the external port GPIO_0 to btn? Could you share a screenshot of your BD?

 

Regards,

 

Florent


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**

View solution in original post

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Observer
Observer
2,281 Views
Registered: ‎11-07-2017

Re: place_design ERROR

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Hi,

 

I am not able to rename GPIO_0 to btn. It throws the warning "Cannot set the parameter 'NAME' on '/processing_system7_0/GPIO_0' - Parameter does not exist."

 

I am attaching the screenshot of my BD.

Hoping to hear from you soon.

 

Thanks & Regards

Vishav

Block_Design.png
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Moderator
Moderator
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Registered: ‎11-09-2015

Re: place_design ERROR

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Hi @vishav26,

 

This is not the port of the Zynq IP that you need to rename but the newly created port of the BD (completely at the right).

 

Regards,

 

Florent


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Observer
Observer
2,242 Views
Registered: ‎11-07-2017

Re: place_design ERROR

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Thanks it worked now

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Observer
Observer
2,217 Views
Registered: ‎11-07-2017

Re: place_design ERROR

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Hi,

I have successfully completed till Step 7 of the attached Lab by Xilinx. When I run the program on hardware, I get a warning that is attached here. Hence, I do not see the expected terminal output.

Also, when I click on Lab1.c code, I see some red lines(attached here). Am I missing something?

 

Thanks & regards

Vishav

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Moderator
Moderator
2,211 Views
Registered: ‎11-09-2015

Re: place_design ERROR

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Hi @vishav26,

 

This is a separated issue and it is an embedded issue please create a new post in the Embedded Development Tools forum.

 

It is unlikely that you will get any further response by continuing this thread.

 

Regards,

 

Florent


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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