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shik1997
Visitor
Visitor
2,300 Views
Registered: ‎01-27-2019

"syntax error near" error in vivado

I am creating a full adder using verilog in vivado.

To implement various functions I am using case statement. 

My code looks like this : 

This is my logicunit.v file

`timescale 1ns / 1ps
 
module logicunit
(
input [5:0] input1,input2,  // inputs to ALU
input [2:0] fxn, // control signal for logical/arithmetic operation
output [5:0] result // output of alu
 
);
 
reg[5:0] alu_result ;
assign result = alu_result ;
 
wire w0,w1,w2 ; // for gteq . 
 
wire c1,c2,c3,c4,c5,c6 ;// for adder circuit 
 
always@(*)
begin 
case ( fxn ) 
 
3'b000 : 
begin 
alu_result = input1 ; 
$display("Input 1") ; 
end 
 
3'b001 : 
begin 
alu_result = input2 ; 
$display("Input 2") ; 
end 
 
 
//3'b010 : 
//begin 
// ; // -A to take 2s complement exor with 1 to generate complement and add 1
//$display("Input 1") ; 
//end 
 
 
//3'b011 : not being used
//begin 
//;  // -B 
//$display("Input 1") ; 
//end 
 
 
3'b100 : 
begin  // A >= B 
 
twobitgteq bit01_unit ( input1[1:0] , input2[1:0] , w0 )  ;  // error comes here. It says error near twobitgteq. 
twobitgteq bit23_unit ( input1[3:2] , input2[3:2] , w1 )  ; 
twobitgteq bit54_unit ( input1[5:4] , input2[5:4] , w2 )  ; 
 
alu_result = w0&w1&w2 ; 
 
$display("Input 1 >= Input B ") ; 
end 
 
 
3'b101 :   // A^B 
begin 
alu_result = input1^input2 ; 
$display("EX-OR operation on A and B") ; 
end 
 
 
3'b110 : // A+B
begin 
sixbitadder f1 ( .x(input1[0]) , .y(input2[0]) , .cin(0) , .sum(alu_result[0]) , .cout(c1) ) ;  // error in these 6 lines also
sixbitadder f2 ( .x(input1[1]) , .y(input2[1]) , .cin(c1) , .sum(alu_result[1]) , .cout(c2) ) ; 
sixbitadder f3 ( .x(input1[2]) , .y(input2[2]) , .cin(c2) , .sum(alu_result[2]) , .cout(c3) ) ;
sixbitadder f4 ( .x(input1[3]) , .y(input2[3]) , .cin(c3) , .sum(alu_result[3]) , .cout(c4) ) ; 
sixbitadder f5 ( .x(input1[4]) , .y(input2[4]) , .cin(c4) , .sum(alu_result[4]) , .cout(c5) ) ; 
sixbitadder f6 ( .x(input1[5]) , .y(input2[5]) , .cin(c5) , .sum(alu_result[5]) , .cout(c6) ) ;
 
$display("Input 1 + Input2") ; 
end 
 
3'b111 : /// A-B 
begin 
sixbitadder f1 ( .x(input1[0]) , .y(input2[0]) , .cin(1) , .sum(alu_result[0]) , .cout(c1) ) ;  // error here also
sixbitadder f2 ( .x(input1[1]) , .y(input2[1]) , .cin(c1) , .sum(alu_result[1]) , .cout(c2) ) ; 
sixbitadder f3 ( .x(input1[2]) , .y(input2[2]) , .cin(c2) , .sum(alu_result[2]) , .cout(c3) ) ;
sixbitadder f4 ( .x(input1[3]) , .y(input2[3]) , .cin(c3) , .sum(alu_result[3]) , .cout(c4) ) ; 
sixbitadder f5 ( .x(input1[4]) , .y(input2[4]) , .cin(c4) , .sum(alu_result[4]) , .cout(c5) ) ; 
sixbitadder f6 ( .x(input1[5]) , .y(input2[5]) , .cin(c5) , .sum(alu_result[5]) , .cout(c6) ) ;
 
 
 
$display("Input 1 - Input2") ;  
end 
 
 
 
endcase
end
endmodule

 

  

Why is the error coming ?

Thanks. 

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2 Replies
shameera
Moderator
Moderator
2,254 Views
Registered: ‎05-31-2017

Hi @shik1997 ,

What syntax error are you facing ? please share the error.

As you are using positional instantiation, please make sure that you are connecting submodule ports correctly.

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richardhead
Scholar
Scholar
2,242 Views
Registered: ‎08-01-2012

You can't instantiate modules inside an always block. They must be instantiated outside Theyre not like c functions, more like chips on a board.