03-10-2019 10:04 AM
I am creating a full adder using verilog in vivado.
To implement various functions I am using case statement.
My code looks like this :
This is my logicunit.v file
Why is the error coming ?
03-13-2019 06:38 AM
03-13-2019 07:47 AM - edited 03-13-2019 07:51 AM
You can't instantiate modules inside an always block. They must be instantiated outside Theyre not like c functions, more like chips on a board.