05-11-2014 06:25 AM
Vivado has undesireable behavoir related to the condition reported as "synthesis and implementation out-of-date".
When I edit a source file vivado indicates "synthesis and implementation out-of-date" so I compile the design. After that, I open the design but it reports that I am opening a design for which synthesis and implementation is out-of-date and asks me if I want to open the design anyway. This requires me to go through the full compile process a second time in order to make vivado happy. That doubles the compile time and is very annoying.
As far as I can tell this happens anytime I touch a VHDL or XDC source. When I check the "more info" button it just tells me that my XDC or VHDL source is modified but that is exactly the reason I compiled the first time.
Can someone provide a workaround or other guidance so I can avoid this annoyance? It is really costing me a lot of time. I am using Vivado 2014.1 on MS Windows 7.
05-11-2014 08:32 AM
This Out-of-Date issue occurs when an IPI design (e.g., design_1.bd in this example) contains IP cores that do not have the latest version of the IP.
This should not be a problem and should not put the project status out of date. However, because of an older IP core version, the IP Integrator will consider the design block as being "stale."
The IPI design block staleness state is determined independent of what was delivered for synthesis / implementation products (e.g., RTL sources, constraints, etc.). Therefore, it should not effect the Vivado project status.
There are two ways to work around this issue:
Doing so will prevent this false run staleness condition from occurring, when opening or closing a project.
05-11-2014 08:15 PM
What are the changes you made to source file?
It is expected that the project runs go out of date when there are changes made to the source files. If you dont want to re-run the process, you can force it up to date as the other poster suggested.