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rtfinch
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Registered: ‎01-06-2016

timing loop during bitstream generation

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I keep getting a timing loop error during bitstream generation (DRC). Changing the code slightly (not involving the signals with the timing loop) causes the timing loop signals to change. It's under sequentially clocked logic and I can't see how there could be a loop. I tried to look it up on the schematic but after an hour or so of searching for the signals I couldn't find them. (The schematic is a giant green blob unless one zooms in about 10x in which case one has to scroll like crazy to see anything.

The code seems to run fine in simulation.

The names of the signals in the timing loop are automatically generated ones by expanded logic. I assume this is for performance improvement.

 

Is there an option I can set to see if it's a genuine timing loop problem ?

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rtfinch
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A valid combinational loop was identified in seemingly unrelated logic. After re-writing the combinational loop to remove the loop, the error message disappeared.

 

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vijayak
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Registered: ‎10-24-2013

Hi @rtfinch

Can you please post the exact error message that you are seeing?

Thanks,Vijay
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rtfinch
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This is using Vivado 17.1 on Windows 10.

 

Message:

[DRC LUTLP-1] Combinatorial Loop Alert: 8 LUT cells form a combinatorial loop. This can create a race condition. Timing analysis may not be accurate. The preferred resolution is to modify the design to remove combinatorial logic loops. If the loop is known and understood, this DRC can be bypassed by acknowledging the condition and setting the following XDC constraint on any net in the loop: 'set_property ALLOW_COMBINATORIAL_LOOPS TRUE [net_nets <myHier/myNet>'. The cells in the loop are: ucpu1/ucpu1/dram0_addr[31]_i_13, ucpu1/ucpu1/dram0_addr[31]_i_18, ucpu1/ucpu1/fcu_argA[63]_i_13, ucpu1/ucpu1/fcu_argB[15]_i_11, ucpu1/ucpu1/fcu_argB[15]_i_15, ucpu1/ucpu1/fcu_argB[15]_i_30, ucpu1/ucpu1/tail1[2]_i_2, and ucpu1/ucpu1/tail1[2]_i_5.

 

They're all _XX expanded signals.

 

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rtfinch
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Here's another timing loop message after some changes to the source code. As you can see there are different cells in the loop this time.

 

[DRC LUTLP-1] Combinatorial Loop Alert: 5 LUT cells form a combinatorial loop. This can create a race condition. Timing analysis may not be accurate. The preferred resolution is to modify the design to remove combinatorial logic loops. If the loop is known and understood, this DRC can be bypassed by acknowledging the condition and setting the following XDC constraint on any net in the loop: 'set_property ALLOW_COMBINATORIAL_LOOPS TRUE [net_nets <myHier/myNet>'. The cells in the loop are: ucpu1/ucpu1/iqentry_v[0]_i_2, ucpu1/ucpu1/iqentry_v[1]_i_2, ucpu1/ucpu1/iqentry_v[2]_i_2, ucpu1/ucpu1/iqentry_v[4]_i_2, and ucpu1/ucpu1/iqentry_v[6]_i_2.

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rtfinch
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Registered: ‎01-06-2016

A valid combinational loop was identified in seemingly unrelated logic. After re-writing the combinational loop to remove the loop, the error message disappeared.

 

View solution in original post

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