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rakesh_bansal
Observer
Observer
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Registered: ‎06-14-2017

vivado 2016.2 abnormal program termination during place_design stage

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Hi,

 

Since yesterday, i'm seeing vivado tool v2016.2 is throwing error at place_design stage.

Out of ten re-trials only once it is going through and finishing routing stage. Rest of times it throws following error :

 

Abnormal program termination (11)
Please check '/fpga/dir/implement/ow_fpga.runs/impl_1/hs_err_pid92822.log' for details

 

 

#
# An unexpected error has occurred (11)
#
Stack:
/lib64/libc.so.6(+0x32660) [0x2ad8fba14660]
/apps/xilinx/vivado/Vivado/2016.2/Vivado/2016.2/lib/lnx64.o/librdi_timing.so(Neptune::Timing::Timer::CRPRDriver(std::vector<int, std::allocator<int> > const*, std::vector<int, std::allocator<int> > const*, int, int, Neptune::Timing::TmRecord*&, Neptune::Timing::TmRecord*&)+0x796) [0x2ad926a48b76]
/apps/xilinx/vivado/Vivado/2016.2/Vivado/2016.2/lib/lnx64.o/librdi_timing.so(Neptune::Timing::Timer::SetupEndRequired(Neptune::Timing::TmNode*)+0x313) [0x2ad926a48fa3]
/apps/xilinx/vivado/Vivado/2016.2/Vivado/2016.2/lib/lnx64.o/librdi_timing.so(Neptune::Timing::Timer::PropagateNodeRequired(Neptune::Timing::TmNode*, bool)+0x7d) [0x2ad926a4ac3d]
/apps/xilinx/vivado/Vivado/2016.2/Vivado/2016.2/lib/lnx64.o/librdi_timing.so(Neptune::Timing::Timer::PropagateNode(Neptune::Timing::Timer::ProcessType, Neptune::Timing::TmNode*, bool)+0x53) [0x2ad926a58c43]
/apps/xilinx/vivado/Vivado/2016.2/Vivado/2016.2/lib/lnx64.o/librdi_timing.so(Neptune::Timing::Timer::Process::ProcessNode(Neptune::Timing::Timer::PropTimingData)+0xb5) [0x2ad926a58d05]
/apps/xilinx/vivado/Vivado/2016.2/Vivado/2016.2/lib/lnx64.o/librdi_timing.so(+0x734289) [0x2ad926a6d289]
/apps/xilinx/vivado/Vivado/2016.2/Vivado/2016.2/lib/lnx64.o/librdi_timing.so(+0x732624) [0x2ad926a6b624]
/apps/xilinx/vivado/Vivado/2016.2/Vivado/2016.2/lib/lnx64.o/libboost_thread.so(+0xeff5) [0x2ad8fd8beff5]
/lib64/libpthread.so.0(+0x7aa1) [0x2ad8fc001aa1]
/lib64/libc.so.6(clone+0x6d) [0x2ad8fbacaaad]

 

I tried to look through other thread also, but of no use. Because sometimes the implementation phase goes through sometimes not!

Can someone help me here?

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1 Solution

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rakesh_bansal
Observer
Observer
5,429 Views
Registered: ‎06-14-2017

Hi All,

 

Just to close on this thread, moving to Vivado v2017.2 resolved the issue.

 

Best Regards,

RB

View solution in original post

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18 Replies
hpoetzl
Voyager
Voyager
3,627 Views
Registered: ‎06-24-2013

Hey @rakesh_bansal

 

I'm not completely sure how to read Vivado stack traces, but it seems to me that the abnormal termination (segfault?) happened in the host libc.

 

Any chance that there was an update to your libc (/lib64/libc.so.6) yesterday?

 

This doesn't mean that there is a bug in libc, it just means that something which worked (maybe because there was a bug :) before doesn't work anymore.

 

Maybe it helps,

Herbert

-------------- Yes, I do this for fun!
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rakesh_bansal
Observer
Observer
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Registered: ‎06-14-2017

hi @hpoetzl,

 

For that i will have to check with IT team, but since yesterday i didn't get any hint of /lib64/libc.so.6/ getting updated. I'm not even sure where is it located. I'm using linux system. Is there a way to figure out update of above mentioned files?

 

But for one moment even if something got changed, why vivado sometimes works and sometimes not?

 

Regards,

Rakesh

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bandi
Moderator
Moderator
3,602 Views
Registered: ‎09-15-2016

Hi @rakesh_bansal,

 

Can you check if this crash is specific to one project or for all the projects in Vivado 2016.2
You can implement any example design to confirm this.

If this crash is specific to one project then please share post synthesized checkpoint file which will be stored in:
<project>/<project>.runs/synth_1/*_synth.dcp

 

Also, can you please share the implementation log file to see at which phase implementation is failing?
you can find this log in impl_1 directory in your project.

 

Further can you please try running in non-project mode and see if you still see the crash? 

 

Thanks & Regards,
Sravanthi B

Thanks & Regards,
Sravanthi B
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vemulad
Xilinx Employee
Xilinx Employee
3,517 Views
Registered: ‎09-20-2012

Hi @rakesh_bansal

 

Similar crash is described in this AR, check if it is applicable https://www.xilinx.com/support/answers/67362.html

 

Try upgrading to latest vivado 2017.2 if possible as 2016.2 is old and multiple crashes like this have been fixed in latest versions.

Thanks,
Deepika.
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rakesh_bansal
Observer
Observer
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Registered: ‎06-14-2017

hi @vemulad,

 

I believe i'm facing this error at different stage. See following log content :

 

Time (s): cpu = 00:01:38 ; elapsed = 00:01:10 . Memory (MB): peak = 2937.215 ; gain = 3.348 ; free physical = 71567 ; free virtual = 129918

Phase 1.1.1.20 Commit IO Placement
Phase 1.1.1.20 Commit IO Placement | Checksum: 6fe47399

Time (s): cpu = 00:01:38 ; elapsed = 00:01:10 . Memory (MB): peak = 2937.215 ; gain = 3.348 ; free physical = 71567 ; free virtual = 129918
Phase 1.1.1 ParallelPlaceIOClockAndInitTop | Checksum: 6fe47399

Time (s): cpu = 00:01:38 ; elapsed = 00:01:10 . Memory (MB): peak = 2937.215 ; gain = 3.348 ; free physical = 71567 ; free virtual = 129918
Phase 1.1 IO Placement/ Clock Placement/ Build Placer Device | Checksum: ba583294

Time (s): cpu = 00:01:38 ; elapsed = 00:01:10 . Memory (MB): peak = 2937.215 ; gain = 3.348 ; free physical = 71567 ; free virtual = 129918

Phase 1.2 Build Placer Netlist Model

Phase 1.2.1 Place Init Design

Phase 1.2.1.1 Make Others
Phase 1.2.1.1 Make Others | Checksum: e3154bd3

Time (s): cpu = 00:01:40 ; elapsed = 00:01:12 . Memory (MB): peak = 2937.215 ; gain = 3.348 ; free physical = 71567 ; free virtual = 129918

Phase 1.2.1.2 Init Lut Pin Assignment
Phase 1.2.1.2 Init Lut Pin Assignment | Checksum: e3154bd3

Time (s): cpu = 00:01:40 ; elapsed = 00:01:12 . Memory (MB): peak = 2937.215 ; gain = 3.348 ; free physical = 71523 ; free virtual = 129874
Abnormal program termination (11)
Please check '/db/lpmcu_tiiavv/bansal_fpga_experiment/OW_FPGA_kurt/implement/ow_fpga.runs/impl_1/hs_err_pid51110.log' for details

 

 

Also, i tried to check the status by 

get_param place.doNopt2

It shows it as '1'.

As suggested in AR, i will try to set to '0' and rerun and see if i face any issue. I will update you on it.

 

@bandi,

 

I'm doing synthesis in synplify_premier_dp but doing implementation in vivado and there is no synth_1 folder.

the log contents are shown above.

place_opt_design phase got completed.

but when place_design phase starts, i see issue.

All the setup currently is in project mode only. Setting it up in non-project mode may take time. 

 

I never faced this issue ever. But i started seeing it couple of days back only. It's taking too much of time to even get design implemented and i'm stuck!

 

Regards,

RB

 

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syedz
Moderator
Moderator
3,496 Views
Registered: ‎01-16-2013

@rakesh_bansal,


Which implementation strategy are you using? Can you try using different implementation strategy and see if it passes?

 

--Syed

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Did you check our new quick reference timing closure guide (UG1292)?
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rakesh_bansal
Observer
Observer
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Registered: ‎06-14-2017

Hi @vemulad,

 

I tried setting 

set_param place.doNopt2 0

But it didn't help.

 

@syedz, i tried changing implementation strategy too, then also it showed same error log.

 

Regards,

RB 

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rakesh_bansal
Observer
Observer
3,452 Views
Registered: ‎06-14-2017

Hi,

 

Can you please suggest something else here?

Everything whatever was suggested is not working.

 

Best Regards,

RB

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vemulad
Xilinx Employee
Xilinx Employee
3,449 Views
Registered: ‎09-20-2012

Hi @rakesh_bansal

 

Some of the crashes related to this phase are fixed in new versions of vivado. Can you try upgrading to vivado 2017.2?

Thanks,
Deepika.
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rakesh_bansal
Observer
Observer
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Registered: ‎06-14-2017

Hi,

 

Can you please let me know the steps to upgrade same installation of vivado v2016.2 to v2017.2?

And just for your information, i was not seeing it for last 2 months. this error started popping up couple of days back only.

 

Best Regards,

RB

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syedz
Moderator
Moderator
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Registered: ‎01-16-2013

@rakesh_bansal,

 

Could be machine specific issue due to new softwares install or upgrade. Try disabling multi threading for implementation and see if it helps:

https://www.xilinx.com/support/answers/50345.html

 

set_param general.maxThreads 1

 

--Syed

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Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.

Did you check our new quick reference timing closure guide (UG1292)?
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vemulad
Xilinx Employee
Xilinx Employee
3,403 Views
Registered: ‎09-20-2012

Hi @rakesh_bansal

 

If you have vivado 2017.2 installed, open the post opt checkpoint (_opt.dcp located in .runs-->impl_1 folder) in vivado 2017.2 and run place_design from tcl console.

 

If this works you can proceed with migration of RTL design to vivado 2017.2. 

Thanks,
Deepika.
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rakesh_bansal
Observer
Observer
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Registered: ‎06-14-2017

Hi @vemulad,

 

One more info which i found in runme.log :

 

WARNING: [DRC 23-20] Rule violation (REQP-1851) BUFGCTRL_I0_I1_cascade_from_clock_buf - Cascaded clock buffers exist in the design with constant CE pin. This may result in large clock skew and timing violations. Cell BUFGCTRL I_mod1/I_mod2/I_mod_clkctl/I_mod_clock_mux_clk1_clk2 I0 pin is driven by another clock buffer clkgen/inst/clk_clk1_keep_RNO.

 

May this be the reason of it tool getting error?

I assumed this is a warning only which shouldn't cause tool any problem. Design is such that i can't avoid this cascading as BUFG output is going to other FFs and at same time BUFG output goes to BUFGCTRL too for clock muxing.

 

Note: With this warning be there in design tool sometimes proceed ahead and finished route stage of implementation.

 

Best Regards,

RB

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vemulad
Xilinx Employee
Xilinx Employee
3,387 Views
Registered: ‎09-20-2012

Hi @rakesh_bansal

 

No, I don't think this is causing placer crash. As message says cascading buffers result in high clock skew and can result in hold failures.

Thanks,
Deepika.
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rakesh_bansal
Observer
Observer
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Registered: ‎06-14-2017

Hi @vemulad,

 

No, i don't have vivado 2017.2 installed separately . And i want to avoid having two versions of vivado on machine too.

That's why i asked if there is a way to upgrade existing vivado v2016.2 to v2017.2?

 

Best Regards,

RB

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rakesh_bansal
Observer
Observer
3,358 Views
Registered: ‎06-14-2017

Hi @syedz,

 

I tried what you told but of no use. (set_param general.maxThreads 1)

Tool was just at same stage for last 2 hours, though it didn't pop up any error message.

 

Regards,

RB

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rakesh_bansal
Observer
Observer
5,430 Views
Registered: ‎06-14-2017

Hi All,

 

Just to close on this thread, moving to Vivado v2017.2 resolved the issue.

 

Best Regards,

RB

View solution in original post

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prathikm
Moderator
Moderator
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Registered: ‎09-15-2016

Hi @rakesh_bansal,

 

Thanks for taking time to update this thread.

 

Thanks & Regards,
Prathik
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