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Visitor
Visitor
1,846 Views
Registered: ‎11-26-2017

vivado 2017 first experience and first project.

good morning

I'm computer science student new to the world FPGA and I'm approaching with Arty board and  I would like to share this experience and be able to implement it properly because unfortunately I found some problem.

As I said, I have no experience with both the program and the technology and I have a Vivado Design Edition Voucher

 

The idea is to implement this code with VHDL: c<=a AND b;   

a , b are two buttons, c is a led;

 

my steps have been:

1. New project:

RTL project with new source of VHDL file type (target language VHDL) and Arty selection in “Default Part. Choose a default xillinx part or board for your project”

In “Define Module. Define a module and specify I/O Ports” I add port name a b c and only the last as output.

 

 

 2. I define the pins, and save on constraints.xdc

Open Elaborate Design> (I/O Planning) >I/O Ports and I define

a ->D9 LVCMOS33

b-> C9 LVCMOS33

c-> H5 LVCMOS33

* in fact I am doubtful about LVCMOS33 on Arty.

 

The project look like this:

VIVprob.jpg

 

3. Run synthesis

LOG:

 

 

Synthesis finished with 0 errors, 0 critical warnings and 0 warnings.
Synthesis Optimization Runtime : Time (s): cpu = 00:00:26 ; elapsed = 00:00:40 . Memory (MB): peak = 703.367 ; gain = 202.785
Synthesis Optimization Complete : Time (s): cpu = 00:00:43 ; elapsed = 00:00:48 . Memory (MB): peak = 703.367 ; gain = 411.313
INFO: [Project 1-571] Translating synthesized netlist
INFO: [Netlist 29-17] Analyzing 2 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-570] Preparing netlist for logic optimization
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
INFO: [Project 1-111] Unisim Transformation Summary:
No Unisim elements were transformed.
 
INFO: [Common 17-83] Releasing license: Synthesis
14 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
synth_design completed successfully
synth_design: Time (s): cpu = 00:00:45 ; elapsed = 00:00:50 . Memory (MB): peak = 711.824 ; gain = 432.297
INFO: [Common 17-1381] The checkpoint 'C:/Users/Francesco/Documents/Xilinx project/and_1/and_1.runs/synth_1/AND_G.dcp' has been generated.
INFO: [runtcl-4] Executing : report_utilization -file AND_G_utilization_synth.rpt -pb AND_G_utilization_synth.pb
report_utilization: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.083 . Memory (MB): peak = 711.824 ; gain = 0.000
INFO: [Common 17-206] Exiting Vivado at Sun Nov 26 10:40:41 2017...

 

 

4. Run implementation

LOG:

              

 

Routing Is Done.
INFO: [Common 17-83] Releasing license: Implementation
49 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
route_design completed successfully
route_design: Time (s): cpu = 00:00:27 ; elapsed = 00:00:24 . Memory (MB): peak = 1123.395 ; gain = 132.539
Writing placer database...
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.092 . Memory (MB): peak = 1123.395 ; gain = 0.000
INFO: [Common 17-1381] The checkpoint 'C:/Users/Francesco/Documents/Xilinx project/and_1/and_1.runs/impl_1/AND_G_routed.dcp' has been generated.
INFO: [runtcl-4] Executing : report_drc -file AND_G_drc_routed.rpt -pb AND_G_drc_routed.pb -rpx AND_G_drc_routed.rpx
Command: report_drc -file AND_G_drc_routed.rpt -pb AND_G_drc_routed.pb -rpx AND_G_drc_routed.rpx
INFO: [DRC 23-27] Running DRC with 2 threads
INFO: [Coretcl 2-168] The results of DRC are in file C:/Users/Francesco/Documents/Xilinx project/and_1/and_1.runs/impl_1/AND_G_drc_routed.rpt.
report_drc completed successfully
INFO: [runtcl-4] Executing : report_methodology -file AND_G_methodology_drc_routed.rpt -pb AND_G_methodology_drc_routed.pb -rpx AND_G_methodology_drc_routed.rpx
Command: report_methodology -file AND_G_methodology_drc_routed.rpt -pb AND_G_methodology_drc_routed.pb -rpx AND_G_methodology_drc_routed.rpx
INFO: [Timing 38-35] Done setting XDC timing constraints.
INFO: [Timing 38-35] Done setting XDC timing constraints.
INFO: [DRC 23-133] Running Methodology with 2 threads
INFO: [Coretcl 2-1520] The results of Report Methodology are in file C:/Users/Francesco/Documents/Xilinx project/and_1/and_1.runs/impl_1/AND_G_methodology_drc_routed.rpt.
report_methodology completed successfully
INFO: [runtcl-4] Executing : report_power -file AND_G_power_routed.rpt -pb AND_G_power_summary_routed.pb -rpx AND_G_power_routed.rpx
Command: report_power -file AND_G_power_routed.rpt -pb AND_G_power_summary_routed.pb -rpx AND_G_power_routed.rpx
WARNING: [Power 33-232] No user defined clocks were found in the design!
Resolution: Please specify clocks using create_clock/create_generated_clock for sequential elements. For pure combinatorial circuits, please specify a virtual clock, otherwise the vectorless estimation might be inaccurate
INFO: [Timing 38-35] Done setting XDC timing constraints.
Running Vector-less Activity Propagation...
 
Finished Running Vector-less Activity Propagation
60 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered.
report_power completed successfully
INFO: [runtcl-4] Executing : report_route_status -file AND_G_route_status.rpt -pb AND_G_route_status.pb
INFO: [runtcl-4] Executing : report_timing_summary -file AND_G_timing_summary_routed.rpt -warn_on_violation  -rpx AND_G_timing_summary_routed.rpx
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1L, Delay Type: min_max.
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs
WARNING: [Timing 38-313] There are no user specified timing constraints. Timing constraints are needed for proper timing analysis.
INFO: [runtcl-4] Executing : report_incremental_reuse -file AND_G_incremental_reuse_routed.rpt
INFO: [Vivado_Tcl 4-545] No incremental reuse to report, no incremental placement and routing data was found.
INFO: [runtcl-4] Executing : report_clock_utilization -file AND_G_clock_utilization_routed.rpt
INFO: [Common 17-206] Exiting Vivado at Sun Nov 26 10:44:30 2017...

 

 5. Generete Bitstream

I also selected:
generate bitstream> bitstream settings ...> bitstream> -bin_file*

LOG:

 

               Synthesis finished with 0 errors, 0 critical warnings and 0 warnings.
Synthesis Optimization Runtime : Time (s): cpu = 00:00:26 ; elapsed = 00:00:40 . Memory (MB): peak = 703.367 ; gain = 202.785
Synthesis Optimization Complete : Time (s): cpu = 00:00:43 ; elapsed = 00:00:48 . Memory (MB): peak = 703.367 ; gain = 411.313
INFO: [Project 1-571] Translating synthesized netlist
INFO: [Netlist 29-17] Analyzing 2 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-570] Preparing netlist for logic optimization
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
INFO: [Project 1-111] Unisim Transformation Summary:
No Unisim elements were transformed.
 
INFO: [Common 17-83] Releasing license: Synthesis
14 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
synth_design completed successfully
synth_design: Time (s): cpu = 00:00:45 ; elapsed = 00:00:50 . Memory (MB): peak = 711.824 ; gain = 432.297
INFO: [Common 17-1381] The checkpoint 'C:/Users/Francesco/Documents/Xilinx project/and_1/and_1.runs/synth_1/AND_G.dcp' has been generated.
INFO: [runtcl-4] Executing : report_utilization -file AND_G_utilization_synth.rpt -pb AND_G_utilization_synth.pb
report_utilization: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.083 . Memory (MB): peak = 711.824 ; gain = 0.000
INFO: [Common 17-206] Exiting Vivado at Sun Nov 26 10:40:41 2017...

 

 5. Load on board

Open Hardware Manager> Auto connect >  secet the hardware device (blue icon) > Program Device… > in Biestream file: I have to select my bitstream file, but I can’t find it.  

 

so I can not figure out where I lose myself in the procedure also doubt at step two.

I hope someone can guide me to easily understand where I am wrong and that I can implement my first example

 

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Highlighted
Moderator
Moderator
1,841 Views
Registered: ‎01-16-2013

@ashman,

 

recheck step 5, You mentioned it is for bitstream generation but the log files gives information on synthesis. 

I believe you are using project (GUI) mode, check if bit file was generated in the folder <project>/<project>.runs/impl_1/**.bit

 

You can also open the implemented design and run "write_bitstream" command in Vivado TCL console to generate bitstream. 

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2017_1/ug835-vivado-tcl-commands.pdf#page=1548

 

Since you mentioned you are new to vivado, I would suggest you to go through the following User guide and tutorial:

Tutorial: https://www.xilinx.com/support/documentation/sw_manuals/xilinx2017_2/ug888-vivado-design-flows-overview-tutorial.pdf

 

User Guide:

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2017_2/ug893-vivado-ide.pdf

 

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2017_2/ug892-vivado-design-flows-overview.pdf

 

--Syed

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