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Newbie
Newbie
4,808 Views
Registered: ‎11-26-2008

warning in NGD. ConstraintSystem:119

Hi,

 

I am using xilinx tools, (xst,ngdbuils,map,par etc)  from command prompt.

 

I wan to observe an internal signal on CRO. This signal is not connected to any input or output ports. I want to observe it w/o chnaging design hierarchy.

So I connected it to one of the FPGA pins in UCF.

 

NET "TOP/MCU/CPUGRP/READY_ETH0" LOC = AL9;

I get following error-

WARNING:ConstraintSystem:119 - Constraint <NET "TOP/MCU/CPUGRP/READY_ETH0" LOC =   AL9;> [mb96v500.ucf(243)]: This constraint cannot be distributed from the   design objects matching 'NET "TOP/MCU/CPUGRP/READY_ETH0"' because those   design objects do not contain or drive any instances of the correct type.

 

 

Is this signal connected to FPGA pin or not?

Is there any way I can connect internal signals to IOs for observation?

 

Thanks in advance

Shruti 

 
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Xilinx Employee
Xilinx Employee
4,781 Views
Registered: ‎08-10-2007

It sounds like you've tried assigning this signal to a Pin, but haven't made it an output of the top level entity.  If you want to do it this way then you need to make the signal an output.  You can do this another way by either adding a probe to your placed and routed NCD file using FPGA Editor or you can use ChipScope to look at the internal signals.
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