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Visitor luoyangjin
Visitor
282 Views
Registered: ‎04-01-2018

warning_pack:2949 (about DQS_BAIS) and error_place:1119

Hello! I want you to help me analyze one warning and one error as follows.

This is my verilog code.

module S20171_1_main(
//*****************SYSTEM SIGNAL*****************************
input rstn,
input clk_66mhz, //66mhz 25mhz

//******************ADC interfaces***************************
input [7:0]adc_ald_p,
input [7:0]adc_ald_n,
input [7:0]adc_ahd_p,
input [7:0]adc_ahd_n,
input adc_adr_p,
input adc_adr_n,

input [7:0]adc_bld_p,
input [7:0]adc_bld_n,
input [7:0]adc_bhd_p,
input [7:0]adc_bhd_n,
// input adc_bdr_p,
// input adc_bdr_n,

input [7:0]adc_cld_p,
input [7:0]adc_cld_n,
input [7:0]adc_chd_p,
input [7:0]adc_chd_n,
// input adc_cdr_p,
// input adc_cdr_n,

input [7:0]adc_dld_p,
input [7:0]adc_dld_n,
input [7:0]adc_dhd_p,
input [7:0]adc_dhd_n
// input adc_ddr_p,
// input adc_ddr_n
//******************
);


wire [7:0]adc_ald;
wire [7:0]adc_ald_delay;


genvar al;
generate
for (al=0; al<8; al=al+1)
begin: ald_loop
//****************Input LVDS 1.8V***************
//****************VCCO of HR bank is 1.8V***************
//****************IOB----IBUFDS***************
//#IBUFDS: Differential Input Buffer
IBUFDS #(
.DIFF_TERM("TRUE"),//differential termination set as FALSE
.IBUF_LOW_PWR("FALSE"),//low_power="TRUE", highest performance is "FALSE"
.IOSTANDARD("LVDS")//specify the input I/O standard
) IBUFDS_inst_ald(
.O(adc_ald[al]),
.I(adc_ald_p[al]),
.IB(adc_ald_n[al])
);
end
endgenerate

wire [7:0]adc_ahd;
wire [7:0]adc_ahd_delay;


genvar ah;
generate
for (ah=0; ah<8; ah=ah+1)
begin: ahd_loop
//****************Input LVDS 1.8V***************
//****************VCCO of HR bank is 1.8V***************
//****************IOB----IBUFDS***************
//#IBUFDS: Differential Input Buffer
IBUFDS #(
.DIFF_TERM("TRUE"),//differential termination set as FALSE
.IBUF_LOW_PWR("FALSE"),//low_power="TRUE", highest performance is "FALSE"
.IOSTANDARD("LVDS")//specify the input I/O standard
) IBUFDS_inst_ahd(
.O(adc_ahd[ah]),
.I(adc_ahd_p[ah]),
.IB(adc_ahd_n[ah])
);
end
endgenerate

wire [7:0]adc_bld;
wire [7:0]adc_bld_delay;


genvar bl;
generate
for (bl=0; bl<8; bl=bl+1)
begin: bld_loop
//****************Input LVDS 1.8V***************
//****************VCCO of HR bank is 1.8V***************
//****************IOB----IBUFDS***************
//#IBUFDS: Differential Input Buffer
IBUFDS #(
.DIFF_TERM("TRUE"),//differential termination set as FALSE
.IBUF_LOW_PWR("FALSE"),//low_power="TRUE", highest performance is "FALSE"
.IOSTANDARD("LVDS")//specify the input I/O standard
) IBUFDS_inst_bld(
.O(adc_bld[bl]),
.I(adc_bld_p[bl]),
.IB(adc_bld_n[bl])
);
end
endgenerate

wire [7:0]adc_bhd;
wire [7:0]adc_bhd_delay;

genvar bh;
generate
for (bh=0; bh<8; bh=bh+1)
begin: bhd_loop
//****************Input LVDS 1.8V***************
//****************VCCO of HR bank is 1.8V***************
//****************IOB----IBUFDS***************
//#IBUFDS: Differential Input Buffer
IBUFDS #(
.DIFF_TERM("TRUE"),//differential termination set as FALSE
.IBUF_LOW_PWR("FALSE"),//low_power="TRUE", highest performance is "FALSE"
.IOSTANDARD("LVDS")//specify the input I/O standard
) IBUFDS_inst_bhd(
.O(adc_bhd[bh]),
.I(adc_bhd_p[bh]),
.IB(adc_bhd_n[bh])
);
end
endgenerate

wire [7:0]adc_cld;
wire [7:0]adc_cld_delay;


genvar cl;
generate
for (cl=0; cl<8; cl=cl+1)
begin: cld_loop
//****************Input LVDS 1.8V***************
//****************VCCO of HR bank is 1.8V***************
//****************IOB----IBUFDS***************
//#IBUFDS: Differential Input Buffer
IBUFDS #(
.DIFF_TERM("TRUE"),//differential termination set as FALSE
.IBUF_LOW_PWR("FALSE"),//low_power="TRUE", highest performance is "FALSE"
.IOSTANDARD("LVDS")//specify the input I/O standard
) IBUFDS_inst_cld(
.O(adc_cld[cl]),
.I(adc_cld_p[cl]),
.IB(adc_cld_n[cl])
);
end
endgenerate

wire [7:0]adc_chd;
wire [7:0]adc_chd_delay;


genvar ch;
generate
for (ch=0; ch<8; ch=ch+1)
begin: chd_loop
//****************Input LVDS 1.8V***************
//****************VCCO of HR bank is 1.8V***************
//****************IOB----IBUFDS***************
//#IBUFDS: Differential Input Buffer
IBUFDS #(
.DIFF_TERM("TRUE"),//differential termination set as FALSE
.IBUF_LOW_PWR("FALSE"),//low_power="TRUE", highest performance is "FALSE"
.IOSTANDARD("LVDS")//specify the input I/O standard
) IBUFDS_inst_chd(
.O(adc_chd[ch]),
.I(adc_chd_p[ch]),
.IB(adc_chd_n[ch])
);


end
endgenerate

wire [7:0]adc_dld;
wire [7:0]adc_dld_delay;


genvar dl;
generate
for (dl=0; dl<8; dl=dl+1)
begin: dld_loop
//****************Input LVDS 1.8V***************
//****************VCCO of HR bank is 1.8V***************
//****************IOB----IBUFDS***************
//#IBUFDS: Differential Input Buffer
IBUFDS #(
.DIFF_TERM("TRUE"),//differential termination set as FALSE
.IBUF_LOW_PWR("FALSE"),//low_power="TRUE", highest performance is "FALSE"
.IOSTANDARD("LVDS")//specify the input I/O standard
) IBUFDS_inst_dld(
.O(adc_dld[dl]),
.I(adc_dld_p[dl]),
.IB(adc_dld_n[dl])
);
end
endgenerate

wire [7:0]adc_dhd;
wire [7:0]adc_dhd_delay;


genvar dh;
generate
for (dh=0; dh<8; dh=dh+1)
begin: dhd_loop
//****************Input LVDS 1.8V***************
//****************VCCO of HR bank is 1.8V***************
//****************IOB----IBUFDS***************
//#IBUFDS: Differential Input Buffer
IBUFDS #(
.DIFF_TERM("TRUE"),//differential termination set as FALSE
.IBUF_LOW_PWR("FALSE"),//low_power="TRUE", highest performance is "FALSE"
.IOSTANDARD("LVDS")//specify the input I/O standard
) IBUFDS_inst_dhd(
.O(adc_dhd[dh]),
.I(adc_dhd_p[dh]),
.IB(adc_dhd_n[dh])
);

end
endgenerate

endmodule

I want to implement the design. When it maps, the warnigs show up and error stop the process. But in my .ucf file, I use IOSTANDARD=LVDS without anything about DQS_BAISE. And the I/Os mentioned in warnings are on the HP bank on XC7K410T-2FFG900 FPGA chip. Why these warnigs come out? And does it matter if I ignore them?
52_4.PNG

The error is like below. There are 64 pairs differential signals, but only one pair differential signal has problem. I have checked the I/O connection: adc_bld_p<6>----AD8 and adc_bld_n<6>---AE8. The positive I/O AND the negetive I/O are right. 

捕获.PNG

Is there anybody who met and solved similiar problem? Please give me some help. Thank you in advance.

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3 Replies
Xilinx Employee
Xilinx Employee
245 Views
Registered: ‎07-16-2008

回复: warning_pack:2949 (about DQS_BAIS) and error_place:1119

Can you also attach the UCF for a look?

-------------------------------------------------------------------------
Don't forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------
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Visitor luoyangjin
Visitor
236 Views
Registered: ‎04-01-2018

回复: warning_pack:2949 (about DQS_BAIS) and error_place:1119

Firstly, thank you for your reply. And this is part of my .UCF file about those I/O.
NET "adc_ahd_p[7]" LOC = AG15;NET "adc_ahd_p[7]" IOSTANDARD = LVDS;NET "adc_ahd_n[7]" LOC = AH15;NET "adc_ahd_n[7]" IOSTANDARD = LVDS;NET "adc_ahd_p[6]" LOC = AB17;NET "adc_ahd_p[6]" IOSTANDARD = LVDS;NET "adc_ahd_n[6]" LOC = AC17;NET "adc_ahd_n[6]" IOSTANDARD = LVDS;NET "adc_ahd_p[5]" LOC = AD19;NET "adc_ahd_p[5]" IOSTANDARD = LVDS;NET "adc_ahd_n[5]" LOC = AE19;NET "adc_ahd_n[5]" IOSTANDARD = LVDS;NET "adc_ahd_p[4]" LOC = AG19;NET "adc_ahd_p[4]" IOSTANDARD = LVDS;NET "adc_ahd_n[4]" LOC = AH19;NET "adc_ahd_n[4]" IOSTANDARD = LVDS;NET "adc_ahd_p[3]" LOC = AF18;NET "adc_ahd_p[3]" IOSTANDARD = LVDS;NET "adc_ahd_n[3]" LOC = AG18;NET "adc_ahd_n[3]" IOSTANDARD = LVDS;NET "adc_ahd_p[2]" LOC = Y16;NET "adc_ahd_p[2]" IOSTANDARD = LVDS;NET "adc_ahd_n[2]" LOC = Y15;NET "adc_ahd_n[2]" IOSTANDARD = LVDS;NET "adc_ahd_p[1]" LOC = Y19;NET "adc_ahd_p[1]" IOSTANDARD = LVDS;NET "adc_ahd_n[1]" LOC = Y18;NET "adc_ahd_n[1]" IOSTANDARD = LVDS;NET "adc_ahd_p[0]" LOC = AA17;NET "adc_ahd_p[0]" IOSTANDARD = LVDS;NET "adc_ahd_n[0]" LOC = AA16;NET "adc_ahd_n[0]" IOSTANDARD = LVDS;NET "adc_ald_p[0]" LOC = AF12;NET "adc_ald_p[0]" IOSTANDARD = LVDS;NET "adc_ald_p[1]" LOC = AE11;NET "adc_ald_p[1]" IOSTANDARD = LVDS;NET "adc_ald_p[2]" LOC = AE10;NET "adc_ald_p[2]" IOSTANDARD = LVDS;NET "adc_ald_p[3]" LOC = AG9;NET "adc_ald_p[3]" IOSTANDARD = LVDS;NET "adc_ald_p[4]" LOC = AF8;NET "adc_ald_p[4]" IOSTANDARD = LVDS;NET "adc_ald_p[5]" LOC = AE13;NET "adc_ald_p[5]" IOSTANDARD = LVDS;NET "adc_ald_p[6]" LOC = AD8;NET "adc_ald_p[6]" IOSTANDARD = LVDS;NET "adc_ald_n[6]" LOC = AE8;NET "adc_ald_n[6]" IOSTANDARD = LVDS;NET "adc_ald_p[7]" LOC = AF7;NET "adc_ald_p[7]" IOSTANDARD = LVDS;NET "adc_bld_p[7]" LOC = AH17;NET "adc_bld_p[7]" IOSTANDARD = LVDS;NET "adc_bld_p[6]" LOC = AK18;NET "adc_bld_p[6]" IOSTANDARD = LVDS;NET "adc_bld_p[5]" LOC = AA13;NET "adc_bld_p[5]" IOSTANDARD = LVDS;NET "adc_bld_p[4]" LOC = AA15;NET "adc_bld_p[4]" IOSTANDARD = LVDS;NET "adc_bld_p[3]" LOC = AE16;NET "adc_bld_p[3]" IOSTANDARD = LVDS;NET "adc_bld_p[2]" LOC = AD17;NET "adc_bld_p[2]" IOSTANDARD = LVDS;NET "adc_bld_p[1]" LOC = AG13;NET "adc_bld_p[1]" IOSTANDARD = LVDS;NET "adc_bld_p[0]" LOC = AA18;NET "adc_bld_p[0]" IOSTANDARD = LVDS;NET "adc_bhd_p[0]" LOC = AB19;NET "adc_bhd_p[0]" IOSTANDARD = LVDS;NET "adc_bhd_p[1]" LOC = AC16;NET "adc_bhd_p[1]" IOSTANDARD = LVDS;NET "adc_bhd_p[2]" LOC = AC14;NET "adc_bhd_p[2]" IOSTANDARD = LVDS;NET "adc_bhd_p[3]" LOC = AH16;NET "adc_bhd_p[3]" IOSTANDARD = LVDS;NET "adc_bhd_p[4]" LOC = AK16;NET "adc_bhd_p[4]" IOSTANDARD = LVDS;NET "adc_bhd_p[5]" LOC = AE15;NET "adc_bhd_p[5]" IOSTANDARD = LVDS;NET "adc_bhd_p[6]" LOC = AF15;NET "adc_bhd_p[6]" IOSTANDARD = LVDS;NET "adc_bhd_p[7]" LOC = AC12;NET "adc_bhd_p[7]" IOSTANDARD = LVDS;NET "adc_chd_p[7]" LOC = AJ3;NET "adc_chd_p[7]" IOSTANDARD = LVDS;NET "adc_chd_p[6]" LOC = AK14;NET "adc_chd_p[6]" IOSTANDARD = LVDS;NET "adc_chd_p[5]" LOC = AJ13;NET "adc_chd_p[5]" IOSTANDARD = LVDS;NET "adc_chd_p[4]" LOC = AH11;NET "adc_chd_p[4]" IOSTANDARD = LVDS;NET "adc_chd_p[3]" LOC = AK11;NET "adc_chd_p[3]" IOSTANDARD = LVDS;NET "adc_chd_p[2]" LOC = AJ9;NET "adc_chd_p[2]" IOSTANDARD = LVDS;NET "adc_chd_p[1]" LOC = AJ8;NET "adc_chd_p[1]" IOSTANDARD = LVDS;NET "adc_chd_p[0]" LOC = AH7;NET "adc_chd_p[0]" IOSTANDARD = LVDS;NET "adc_cld_p[0]" LOC = AC2;NET "adc_cld_p[0]" IOSTANDARD = LVDS;NET "adc_cld_p[1]" LOC = AD2;NET "adc_cld_p[1]" IOSTANDARD = LVDS;NET "adc_cld_p[2]" LOC = AF3;NET "adc_cld_p[2]" IOSTANDARD = LVDS;NET "adc_cld_p[3]" LOC = AG4;NET "adc_cld_p[3]" IOSTANDARD = LVDS;NET "adc_cld_p[4]" LOC = AJ1;NET "adc_cld_p[4]" IOSTANDARD = LVDS;NET "adc_cld_p[5]" LOC = AH2;NET "adc_cld_p[5]" IOSTANDARD = LVDS;NET "adc_cld_p[6]" LOC = AK5;NET "adc_cld_p[6]" IOSTANDARD = LVDS;NET "adc_cld_p[7]" LOC = AH6;NET "adc_cld_p[7]" IOSTANDARD = LVDS;NET "adc_dld_p[7]" LOC = AA11;NET "adc_dld_p[7]" IOSTANDARD = LVDS;NET "adc_dld_p[6]" LOC = AA8;NET "adc_dld_p[6]" IOSTANDARD = LVDS;NET "adc_dld_p[5]" LOC = AE4;NET "adc_dld_p[5]" IOSTANDARD = LVDS;NET "adc_dld_p[4]" LOC = AG2;NET "adc_dld_p[4]" IOSTANDARD = LVDS;NET "adc_dld_p[3]" LOC = AC7;NET "adc_dld_p[3]" IOSTANDARD = LVDS;NET "adc_dld_p[2]" LOC = AH4;NET "adc_dld_p[2]" IOSTANDARD = LVDS;NET "adc_dld_p[1]" LOC = AE5;NET "adc_dld_p[1]" IOSTANDARD = LVDS;NET "adc_dld_p[0]" LOC = AJ6;NET "adc_dld_p[0]" IOSTANDARD = LVDS;NET "adc_dhd_p[0]" LOC = AD6;NET "adc_dhd_p[0]" IOSTANDARD = LVDS;NET "adc_dhd_p[1]" LOC = AD9;NET "adc_dhd_p[1]" IOSTANDARD = LVDS;NET "adc_dhd_p[2]" LOC = AB10;NET "adc_dhd_p[2]" IOSTANDARD = LVDS;NET "adc_dhd_p[3]" LOC = AA12;NET "adc_dhd_p[3]" IOSTANDARD = LVDS;NET "adc_dhd_p[4]" LOC = Y11;NET "adc_dhd_p[4]" IOSTANDARD = LVDS;NET "adc_dhd_p[5]" LOC = AE1;NET "adc_dhd_p[5]" IOSTANDARD = LVDS;NET "adc_dhd_p[6]" LOC = AD4;NET "adc_dhd_p[6]" IOSTANDARD = LVDS;NET "adc_dhd_p[7]" LOC = AC5;NET "adc_dhd_p[7]" IOSTANDARD = LVDS;

By the way, in my .V file, I use the ila and icon IPs. When I didn't use those signals-adc_ald[7:0], this error didn't come out.

As so far, I didn't know the reason. 

Thank you again~

F

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Xilinx Employee
Xilinx Employee
224 Views
Registered: ‎07-16-2008

回复: warning_pack:2949 (about DQS_BAIS) and error_place:1119

From your attached UCF, the IO placement of the ports in question is not like what you mentioned.

NET "adc_bld_p[6]" LOC = AK18;

This is the N-side of a pair of differential package pins. So the error message looks valid.

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