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why latches are considered bad???

Observer
Posts: 21
Registered: ‎01-18-2010

why latches are considered bad???

why latches are considered bad in any design and how/why they are created?

 

Thnx in advance

Hamza Ali

Scholar
Posts: 1,119
Registered: ‎10-05-2010

Re: why latches are considered bad???

If this is a homework question, consult your class notes or ask your instructor.

 

Gabor gave an excellent description of why latches should be avoided here (have you tried searching the forum?).

 

Your HDL textbook should tell you how and why they're created. Here's an excerpt from FPGA Prototyping by Verilog Examples (Chu 2008):

 

lncomplete branch and incomplete output assignment

 

The output of a combinational circuit is a function of input only and the circuit should not contain any internal state (i.e., memory). One common error with an always block is the inference of unintended memory in a combinational circuit. The Verilog standard specifies that a variable will keep its previous value if it is not assigned a value in an always block. During synthesis, this infers an internal state (via a closed feedback loop) or a memory element (such as a latch).

 

Here's a link to the page on Google Books.

 

Teacher
Posts: 8,355
Registered: ‎07-21-2009

Re: why latches are considered bad???

[ Edited ]

why latches are considered bad in any design and how/why they are created?

 

Latches are not bad.  They are very very good, in fact.  Most of the very highest performance mainframes and supercomputers of the 1960s, 70s, and 80s were based largely on the use of latches.  I have personally helped design several mainframe computers and array processors with them.  At the risk of over-generalising, their greatest benefit is improved machine cycle time in systems where system clock skew is a significant fraction of the system clock cycle time (period).

 

Having said that, latches are a very poor match for logic systems implemented in FPGAs.  The performance benefit of latches described above is not realised in FPGA designs because on-chip clock distribution skew is effectively nil.

 

Latches are considered 'bad' because

  • Latches are almost always unintentionally inferred by poorly written source code
  • FPGA timing tools (and timing based place/route algorithms) are single-mindedly oriented to register-based design

 

-- Bob Elkind

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Teacher
Posts: 2,113
Registered: ‎09-09-2010

Re: why latches are considered bad???

"Latches are almost always unintentionally inferred by poorly written source code"

... or use of a MicroBlaze processor core.

------------------------------------------
"If it don't work in simulation, it won't work on the board."
Teacher
Posts: 8,355
Registered: ‎07-21-2009

Latches in MicroBlaze ????

... or use of a MicroBlaze processor core.

 

Latches are used in the MicroBlaze core?  That's interesting!  I've not yet used MicroBlaze, and I would never have guessed right on this point.

 

Are latches used profusely, or just in one area or application, or is it an optional selection?

 

-- Bob Elkind

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Scholar
Posts: 1,119
Registered: ‎10-05-2010

Re: Latches in MicroBlaze ????


Are latches used profusely, or just in one area or application, or is it an optional selection?


I haven't used it outside of the evaluation period, but UG081 says:

"By using the parameter C_INTERRUPT_IS_EDGE, the external interrupt can either be set to level-sensitive or edge-sensitive:" (p. 68)

Maybe there are a few other places they're used, too. An old post by rcingham on comp.arch.fpga mentions that there are three latches in one particular 10.1 era MicroBlaze core.

 

On a similar topic, another exciting one to look out for is the gated clock warnings when using ChipScope Pro!

 

Teacher
Posts: 8,355
Registered: ‎07-21-2009

Re: Latches in MicroBlaze ????

I haven't used it outside of the evaluation period, but UG081 says:

"By using the parameter C_INTERRUPT_IS_EDGE, the external interrupt can either be set to level-sensitive or edge-sensitive:" (p. 68)

What you describe does not necessarily infer a latch.

 

-- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.
Xilinx Employee
Posts: 5,114
Registered: ‎01-03-2008

Re: Latches in MicroBlaze ????

> On a similar topic, another exciting one to look out for is the gated clock warnings when using ChipScope Pro!

 

This is on purpose in order to detect edge transitions for the DATA bus, TRIGGER bus, or for the inputs of a VIO core where the logic net is used as a clock input to registers.  The timing on these path is not relevant.

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