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Explorer
Explorer
153 Views
Registered: ‎10-12-2016

why top/bottom side bug's are usable for bottom/top side clock region resources ?

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HI Friends, 

I got error like PLL in bottom side should use bottom side BUFG's. why this limitation ? 

How to lock and which to lock for my bottom side PLL ?

For any help or suggestions are highly appreciated. 

Thank You 

S Sampath

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1 Solution

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Xilinx Employee
Xilinx Employee
121 Views
Registered: ‎05-08-2012

Re: why top/bottom side bug's are usable for bottom/top side clock region resources ?

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HI @ssampath.

The 7-Series architecture was designed so that the top/bottom BUFG site would drive loads in this half of the device. It might be possible to use a CLOCK_DEDICTATED_ROUTE=FALSE to see what the timing degradation is, but this would only be recommended as a test. The below Clocking Resources Guide has more information on the BUFG clocking.

https://www.xilinx.com/support/documentation/user_guides/ug472_7Series_Clocking.pdf#PAGE=36

constraining cells such as PLLs or MMCMs can be accomplished with a LOC constraint. The following is an example of the syntax.

set_property LOC PLLE2_ADV_X*Y* [get_cells <name_of_pll_instance>]

As to which PLL, I would select the PLL within the same clock region as the I/O driving it.


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1 Reply
Xilinx Employee
Xilinx Employee
122 Views
Registered: ‎05-08-2012

Re: why top/bottom side bug's are usable for bottom/top side clock region resources ?

Jump to solution

HI @ssampath.

The 7-Series architecture was designed so that the top/bottom BUFG site would drive loads in this half of the device. It might be possible to use a CLOCK_DEDICTATED_ROUTE=FALSE to see what the timing degradation is, but this would only be recommended as a test. The below Clocking Resources Guide has more information on the BUFG clocking.

https://www.xilinx.com/support/documentation/user_guides/ug472_7Series_Clocking.pdf#PAGE=36

constraining cells such as PLLs or MMCMs can be accomplished with a LOC constraint. The following is an example of the syntax.

set_property LOC PLLE2_ADV_X*Y* [get_cells <name_of_pll_instance>]

As to which PLL, I would select the PLL within the same clock region as the I/O driving it.


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Don’t forget to reply, kudo, and accept as solution.
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