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gd
Observer
Observer
610 Views
Registered: ‎09-02-2020

xpm_memory_sdpram not recognized in Vivado synthesis

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I get the following error message

[Synth 8-5826] no such design unit 'xpm_memory_sdpram' in library 'xpm'

attempting to synthesize this code (even after issuing "auto_detect_xpm" as per AR#70017).

-----------------------------------------------------------------------
-- UltraRAM dual port memory instantiation
-----------------------------------------------------------------------
u0_xpm_memory_sdpram : entity xpm.xpm_memory_sdpram
generic map (
-- Common module generics
MEMORY_SIZE => MEMORY_SIZE,
MEMORY_PRIMITIVE => MEMORY_PRIMITIVE,
CLOCKING_MODE => CLOCKING_MODE,
MEMORY_INIT_FILE => MEMORY_INIT_FILE,
MEMORY_INIT_PARAM => MEMORY_INIT_PARAM,
USE_MEM_INIT => 0,
WAKEUP_TIME => WAKEUP_TIME,
MESSAGE_CONTROL => 1, --integer;
ECC_MODE => ECC_MODE,
AUTO_SLEEP_TIME => 0, --Do not Change
USE_EMBEDDED_CONSTRAINT => 0, --integer: 0,1
MEMORY_OPTIMIZATION => MEMORY_OPTIMIZATION,
-- Port A module generics
WRITE_DATA_WIDTH_A => MEM_DATA_WIDTH, --positive integer
BYTE_WRITE_WIDTH_A => MEM_DATA_WIDTH, --integer; 8, 9, or WRITE_DATA_WIDTH_A value
ADDR_WIDTH_A => LOG2_SAMPLES, --positive integer
RST_MODE_A => RST_MODE_A,
-- Port B module generics
READ_DATA_WIDTH_B => MEM_DATA_WIDTH, --positive integer
ADDR_WIDTH_B => LOG2_SAMPLES, --positive integer
RST_MODE_B => RST_MODE_B,
READ_RESET_VALUE_B => READ_RESET_VALUE_B, --string
READ_LATENCY_B => 1, --non-negative integer
WRITE_MODE_B => WRITE_MODE_B,
SIM_ASSERT_CHK => 1
)
port map (
-- Common module ports
sleep => LOGIC_ZERO,
-- Port A module ports
clka => ACLK,
ena => amc_ena,
wea => amc_wea,
addra => std_logic_vector(amc_addr_i),
dina => amc_data_i(i),
injectsbiterra => LOGIC_ZERO,
injectdbiterra => LOGIC_ZERO,
-- Port B module ports
clkb => ACLK,
rstb => areset,
enb => amc_enb,
regceb => LOGIC_ONE,
addrb => std_logic_vector(amc_addr_o),
doutb => amc_data_o(i),
sbiterrb => open,
dbiterrb => open
);

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Accepted Solutions
amaccre
Moderator
Moderator
473 Views
Registered: ‎04-24-2013

hi @gd 

Change the line 351 from:
u0_xpm_memory_sdpram : entity xpm.xpm_memory_sdpram

to:
u0_xpm_memory_sdpram : xpm_memory_sdpram

Once I did this, synthesis ran without the xpm error:

amaccre_0-1611160112919.png

 

Also the wea in the XPM should be a vector and not a bit, from the description in the header:

wea => wea -- WRITE_DATA_WIDTH_A/BYTE_WRITE_WIDTH_A-bit input: Write enable vector
-- for port A input data port dina. 1 bit wide when word-wide writes
-- are used. In byte-wide write configurations, each bit controls the
-- writing one byte of dina to address addra. For example, to
-- synchronously write only bits [15-8] of dina when WRITE_DATA_WIDTH_A
-- is 32, wea would be 4'b0010.

Best Regards
Aidan

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6 Replies
hongh
Moderator
Moderator
580 Views
Registered: ‎11-04-2010

Please try the workaround in AR-67815

 

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gd
Observer
Observer
547 Views
Registered: ‎09-02-2020

After applying the workaround in AR-67815 I still get the error message

[Synth 8-5826] no such design unit 'xpm_memory_sdpram' in library 'xpm'

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amaccre
Moderator
Moderator
501 Views
Registered: ‎04-24-2013

Hi @gd 

Did you add the references to the library as per the language template i.e.:

-- Copy the following two statements and paste them before the
-- Entity declaration, unless they already exist.

Library xpm;
use xpm.vcomponents.all;

Best Regards
Aidan

 

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gd
Observer
Observer
483 Views
Registered: ‎09-02-2020

The references to the library are instantiated while the error persists.

I've attached the vhdl file for reference.

 

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amaccre
Moderator
Moderator
474 Views
Registered: ‎04-24-2013

hi @gd 

Change the line 351 from:
u0_xpm_memory_sdpram : entity xpm.xpm_memory_sdpram

to:
u0_xpm_memory_sdpram : xpm_memory_sdpram

Once I did this, synthesis ran without the xpm error:

amaccre_0-1611160112919.png

 

Also the wea in the XPM should be a vector and not a bit, from the description in the header:

wea => wea -- WRITE_DATA_WIDTH_A/BYTE_WRITE_WIDTH_A-bit input: Write enable vector
-- for port A input data port dina. 1 bit wide when word-wide writes
-- are used. In byte-wide write configurations, each bit controls the
-- writing one byte of dina to address addra. For example, to
-- synchronously write only bits [15-8] of dina when WRITE_DATA_WIDTH_A
-- is 32, wea would be 4'b0010.

Best Regards
Aidan

------------------------------------------------------------------------------------------------------------------
Please mark the Answer as "Accept as solution" if this answered your question
Give Kudos to a post which you think is helpful and may help other users
------------------------------------------------------------------------------------------------------------------

View solution in original post

gd
Observer
Observer
465 Views
Registered: ‎09-02-2020

Thank you Aidan!

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