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Contributor
Contributor
3,018 Views
Registered: ‎09-19-2018

DPU TRD for ZCU104 ?

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Hi, I would like to use DPU TRD in ZCU104 but at the download page (https://www.xilinx.com/products/design-tools/ai-inference/ai-developer-hub.html#edge) I can only see this file: zcu102-dpu-trd-2018-2-190322.zip, which seems to be the IP for ZCU102 board.

So my question is: is this IP available for ZCU104 board ?

Regards.

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1 Solution

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Adventurer
Adventurer
2,409 Views
Registered: ‎06-09-2015

Re: DPU TRD for ZCU104 ?

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Hello everyone, we have build and tested the "DPU TRD for ZCU104" as the PG338 Guide and Tcl file provided by @jheaton. We also have published an article on it and showed up the results there. Please follow this article [step-by-step tutorial] for implementing "DPU TRD on ZCU104": DPU TRD for ZCU104Here is the "Demo Test -DPU TRD for ZCU104" download link [File size: 141MB] : https://drive.google.com/open?id=1AyxDg1TRwMIcIaAdqrQdf2cvw4Nj0uen . This project also has been tested by @shairva  on the ZCU104 FPGA Board.

Regards,
krishna@logictronix.com
19 Replies
Xilinx Employee
Xilinx Employee
2,967 Views
Registered: ‎03-21-2008

Re: DPU TRD for ZCU104 ?

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The DPU TRD can be retargeted to the ZCU104 board.

Vivado:

I have attached a script to create the project in 2018.2. Place it in the pl dir and execute vivado -source zcu104.tcl

The main changes were:

1) Changing project part to ZCU104 Evaluation Board.

2) Applying board presets to ZyncUltraScale+ block in IP Integrator.

3) Changing the DPU options to use 20 Ultra Rams. This is needed becuase the device on the ZCU104 has less brams than the device on the ZCU102.

4) Increasing place and route effort levels for Vivado.

Petalinux

You can use the existing zcu102-dpu-trd-v2018.2 bsp for the Petalinux project and follow the TRD instructions. There is one change you have to make:

1) In the petalinux-config step you will need to change the machine name to zcu104-revc: DTG Settings -> MACHINE_NAME = zcu100-revc

 

Xilinx Employee
Xilinx Employee
2,960 Views
Registered: ‎03-21-2008

Re: DPU TRD for ZCU104 ?

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Correction:

The last line should be:

1) In the petalinux-config step you will need to change the machine name to zcu104-revc: DTG Settings -> MACHINE_NAME = zcu104-revc

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Contributor
Contributor
2,930 Views
Registered: ‎09-19-2018

Re: DPU TRD for ZCU104 ?

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I think that file has some hard-coded paths because I'm getting this error:

Can you help me?

 

Captura.PNG

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Xilinx Employee
Xilinx Employee
2,912 Views
Registered: ‎03-21-2008

Re: DPU TRD for ZCU104 ?

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First run the script ./scripts/trd_prj.tcl, this will create a project for the zu102 and will create the file top_wrapper.v

Then run the zcu104 script, this will create a new project for the zcu104. This script will create the project  pl/zcu104, and when this completes you can delete the zcu102 project files in pl/prj.

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Contributor
Contributor
2,877 Views
Registered: ‎09-19-2018

Re: DPU TRD for ZCU104 ?

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Dear @jheaton ,

I've followed your instructions:

1- Run ./scripts/trd_prj.tcl

2- Run zcu104.tcl

Until here, everything was OK

3- Generate Bitstream <--- Here I got these problems:

Captura.PNG

If we go to the timing report:

Captura1.PNG

What are your recommendations to fix that ?

Thanks in advance

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Xilinx Employee
Xilinx Employee
2,853 Views
Registered: ‎03-21-2008

Re: DPU TRD for ZCU104 ?

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It meets timing in Vivado 2018.2. What versio of Vivado did you use?

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Contributor
Contributor
2,843 Views
Registered: ‎09-19-2018

Re: DPU TRD for ZCU104 ?

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I'm using Vivado 2018.3

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Observer scanas
Observer
2,820 Views
Registered: ‎02-02-2018

Re: DPU TRD for ZCU104 ?

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Dear @jheaton ,

I've installed Vivado 2018.2 and run the synthesis, and I am not meeting the timing constraints.

Can you please help me ?

Captura.PNG

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Xilinx Employee
Xilinx Employee
2,816 Views
Registered: ‎03-21-2008

Re: DPU TRD for ZCU104 ?

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Make sure the Synth Startgey is set to Flow_PerOptimzed_high and the Implemenation tio  Performance_ExporePostRoutePhysOpt. 

Please attach the runme.log file from the impl_1 dir.

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Contributor
Contributor
2,638 Views
Registered: ‎09-19-2018

Re: DPU TRD for ZCU104 ?

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With Synth Startgey set to Flow_PerOptimzed_high I could not meet the timing constraints at the synthesis, why? do you know that?

But then, using Performance_ExporePostRoutePhysOpt at the implementation, I could meet the timing constraints.

I've used Vivado 2018.2

Captura2jpg.jpg

Thank you

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Contributor
Contributor
2,615 Views
Registered: ‎09-19-2018

Re: DPU TRD for ZCU104 ?

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@jheaton why it does not meet the timing constraints in Vivado 2018.3 ?

Is there any solution for that?

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Xilinx Employee
Xilinx Employee
2,610 Views
Registered: ‎03-21-2008

Re: DPU TRD for ZCU104 ?

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The timing results post Synthesis are using estimated delays for routing based on wire length, and there will be differnces from the final timing post route.

A small negative WNS > - 500ps post Synthesis is generally okay, and often Vivado can still meet timing. A large negative WNS after Sythesis means the design is very unlikely to meet timing and you need to change the design or Sythesis settings. Its also okay to have a  small negative WHS sfter Synthesis as well, the router typiclally fix these hold errors. 

The DPU TRD was tested on Vivado 2018.2 and Petalinux 2018.2. I recommend staying with this version of Vivado, until the next version of the DPU comes.

A new version of the DPU is comming out very soon.

 

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Adventurer
Adventurer
2,410 Views
Registered: ‎06-09-2015

Re: DPU TRD for ZCU104 ?

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Hello everyone, we have build and tested the "DPU TRD for ZCU104" as the PG338 Guide and Tcl file provided by @jheaton. We also have published an article on it and showed up the results there. Please follow this article [step-by-step tutorial] for implementing "DPU TRD on ZCU104": DPU TRD for ZCU104Here is the "Demo Test -DPU TRD for ZCU104" download link [File size: 141MB] : https://drive.google.com/open?id=1AyxDg1TRwMIcIaAdqrQdf2cvw4Nj0uen . This project also has been tested by @shairva  on the ZCU104 FPGA Board.

Regards,
krishna@logictronix.com
Observer gwjjj35
Observer
1,842 Views
Registered: ‎04-16-2019

Re: DPU TRD for ZCU104 ?

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Is zcu104.tcl released for DPU1.4 IP?I need it badly.

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Observer gwjjj35
Observer
1,835 Views
Registered: ‎04-16-2019

Re: DPU TRD for ZCU104 ?

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If you follow the steps, then vivado generated. HDF files for ZCU104 are not used?

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Observer cumtdaibo
Observer
898 Views
Registered: ‎05-31-2019

Re: DPU TRD for ZCU104 ?

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Thanks for your instruction! Is there a plan to retarget the DPU design to Avnet UltraZad Board? Which is use ZU11EG.

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Adventurer
Adventurer
641 Views
Registered: ‎05-27-2019

Re: DPU TRD for ZCU104 ?

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@cumtdaibo wrote:

Thanks for your instruction! Is there a plan to retarget the DPU design to Avnet UltraZad Board? Which is use ZU11EG.


UltraZad ?  Do you mean UltraZed? 

I also want to know how can I transfer a DPU from ZCU102 to other UltraScale MPSoC platform? such as ZU11EG, which @cumtdaibo mentioned above.

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Observer cumtdaibo
Observer
593 Views
Registered: ‎05-31-2019

Re: DPU TRD for ZCU104 ?

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Not Ultrazed, I mean the UltraZ AD board from AVNET.
捕获.JPG
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Adventurer
Adventurer
587 Views
Registered: ‎05-27-2019

Re: DPU TRD for ZCU104 ?

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Hi @cumtdaibo 

I search this topic yesterday, share with you:

Image_20190924-153404.png

and Zynq 7000 family

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