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Contributor
Contributor
207 Views
Registered: ‎03-06-2019

DPU output to another module

Hi,

I want to connect DPU output to another FPGA module through axi without writing it to DRAM. How can I access that output?

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4 Replies
Xilinx Employee
Xilinx Employee
165 Views
Registered: ‎03-27-2013

回复: DPU output to another module

Hi @baharlab ,

 

We have a axi_c2c IP can handle the axi traffic between 2 FPGA chips. You can find detailed information from PG067.

But you would need to handle the extra hardware requirement, system addresssing, longer latency and even some custom modification for your ML application code.

This may spend you a lot of time to design, debug and verify. I would not recommend you to do that if you have other choice.

 

Best Regards,
Jason
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Observer naz_sw
Observer
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Registered: ‎02-25-2019

回复: DPU output to another module

@jasonwu  I think the original question is "how to gain access to the DPU output without writing it to RAM". In my case, I am not planing to stream this data to another chip, but instead, use the output and process it in PL. What would be a valid approach to intercept the DPU output data?

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Xilinx Employee
Xilinx Employee
102 Views
Registered: ‎03-27-2013

回复: DPU output to another module

Hi @naz_sw ,

 

Thanks for reminding.

I can see the original question is "I want to connect DPU output to another FPGA module through axi without writing it to DRAM"

If customer want to transfer "axi" to "another FPGA" the C2C would be the easy sollution which Xilinx can provide and as said before the IP would introduce high lantency and additional hardware cost.

For your new question the quick answer would be an axi_slave in PL. Like axi_bram controller, or some logic with an axi_slave written by yourself.

But the problem would be how to tell DPU the slave is a "target RAM" to store the ConvNet output data.


BTW if the output data of your ConvNet is not so complex I would just suggest you to store it in to DDR first and let CPU handle the data movement. Comparing with the high loading during ConvNet caculation it would not be the key cost to read the output data and send it to somewhere else. And that would save you a lot of time for debugging.

Hope the suggestions can help. :-)

And since this is a new topic if you have further question or if I have missed anything here I would suggest you to create a new post with your topic so that someone else may provide more helpful suggestions.

Best Regards,
Jason
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Observer naz_sw
Observer
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Registered: ‎02-25-2019

回复: DPU output to another module

@jasonwu  Thank you. I was just wondering if I could deroute the DPU data from the RAM and accellerate the DPU output in the PL.

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