cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
Newbie
Newbie
428 Views
Registered: ‎05-14-2019

32Gb LPDDR4 Quad die, Dual Channel, Dual Rank for MPSOC

Jump to solution

Hi,

I would like to know MPSOC supports 32Gb LPDDR4 MT53D1024M32D4DT-053 WT:D which is quad die, dual channel, dual rank.

Do you have any reference designs containing this memory with MPSOC? 

Thanks

1 Solution

Accepted Solutions
Moderator
Moderator
371 Views
Registered: ‎06-29-2011

Hi @e.b 

The ability for the PS controller to support a quad die LPDDR4 device depends on the specifics of the device you want to use. From there you will need to check DS925 for FMAX we can support. DS925 only lists two operating points for the LPDDR4 interface; either a single die package or a dual die package. For our supported memory conditions please refer to UG1085, Table 17-1.

The following is referring to UG582 which is the PCB design guide. When you get to something like a MT53D1024M32D4 which has 4 die it's basically the dual rank version of the MT53D512M32D2. The MT53D512M32D2 will be connected like Table 2-36: Signal Connection Matrix for x32 Dual Channel LPDDR4 SDP without ECC while the MT53D1024M32D4 will be connected like Table 2-37: Signal Connection Matrix for x32 Dual Channel LPDDR4 DDP without ECC. This is because the MT53D512M32D2 has a separate die for each 16-bit channel but effectively operates as a monolithic die (SDP) device. Following the same thought process the MT53D1024M32D4 adds an additional physical rank to the MT53D512M32D2 topology, so it can be treated as a Dual Die Package (DDP).

As an example of quad die device that won't work is the MT53B1024M32D4 because each channel for each die is only 8-bits wide, not supported.

Now from a loading perspective the MT53D512M32D2 will have the same signal loads as a monolithic device but there are two discrete die in the package so that may mean additional channel loss from the package routing and noise. This type of device wasn't tested so it may be possible to achieve 2400Mbps without any issue but it's also possible you'll have to derate the interface a bit for these additional channel losses. For something like the MT53D1024M32D4 you're definitely derating to 2133Mbps and it may be necessary to go slower for the same reasons. Refer to DS925 Table 30.

Doc References:
DS925, Zynq US+ MPSoC Datasheet - https://www.xilinx.com/support/documentation/data_sheets/ds925-zynq-ultrascale-plus.pdf
UG583, US PCB Design User Guide - https://www.xilinx.com/support/documentation/user_guides/ug583-ultrascale-pcb-design.pdf
UG1085, Zynq US+ Device TRM - https://www.xilinx.com/support/documentation/user_guides/ug1085-zynq-ultrascale-trm.pdf
PG201, Zynq US+ MPSoC Processing System - https://www.xilinx.com/support/documentation/ip_documentation/zynq_ultra_ps_e/v3_3/pg201-zynq-ultrascale-plus-processing-system.pdf
UG1209, Zynq US+ MPSoC: Embedded Design Tutorial - https://www.xilinx.com/support/documentation/sw_manuals/xilinx2020_1/ug1209-embedded-design-tutorial.pdf

We do not have specific reference designs for this but once you have created your board you can test this with a simple design with just a Zynq US+ MPSoC block dropped into IPI and configured the PS DDR and then export the XSA and run the memory test and Zynq US+ MPSoC DRAM Diagnostics test applications in SDK/Vitis. you can do this with nothing in PL logic and so there is no bitstream required. This is detailed in UG1209 which describes running a hello world application. All you need to do is run the memory tests instead after following this guide. PG201 can be used to see how to configure the PS DDR using an example for DDR3L but same theory applies.

-------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------

Kind regards,
Gareth

View solution in original post

1 Reply
Moderator
Moderator
372 Views
Registered: ‎06-29-2011

Hi @e.b 

The ability for the PS controller to support a quad die LPDDR4 device depends on the specifics of the device you want to use. From there you will need to check DS925 for FMAX we can support. DS925 only lists two operating points for the LPDDR4 interface; either a single die package or a dual die package. For our supported memory conditions please refer to UG1085, Table 17-1.

The following is referring to UG582 which is the PCB design guide. When you get to something like a MT53D1024M32D4 which has 4 die it's basically the dual rank version of the MT53D512M32D2. The MT53D512M32D2 will be connected like Table 2-36: Signal Connection Matrix for x32 Dual Channel LPDDR4 SDP without ECC while the MT53D1024M32D4 will be connected like Table 2-37: Signal Connection Matrix for x32 Dual Channel LPDDR4 DDP without ECC. This is because the MT53D512M32D2 has a separate die for each 16-bit channel but effectively operates as a monolithic die (SDP) device. Following the same thought process the MT53D1024M32D4 adds an additional physical rank to the MT53D512M32D2 topology, so it can be treated as a Dual Die Package (DDP).

As an example of quad die device that won't work is the MT53B1024M32D4 because each channel for each die is only 8-bits wide, not supported.

Now from a loading perspective the MT53D512M32D2 will have the same signal loads as a monolithic device but there are two discrete die in the package so that may mean additional channel loss from the package routing and noise. This type of device wasn't tested so it may be possible to achieve 2400Mbps without any issue but it's also possible you'll have to derate the interface a bit for these additional channel losses. For something like the MT53D1024M32D4 you're definitely derating to 2133Mbps and it may be necessary to go slower for the same reasons. Refer to DS925 Table 30.

Doc References:
DS925, Zynq US+ MPSoC Datasheet - https://www.xilinx.com/support/documentation/data_sheets/ds925-zynq-ultrascale-plus.pdf
UG583, US PCB Design User Guide - https://www.xilinx.com/support/documentation/user_guides/ug583-ultrascale-pcb-design.pdf
UG1085, Zynq US+ Device TRM - https://www.xilinx.com/support/documentation/user_guides/ug1085-zynq-ultrascale-trm.pdf
PG201, Zynq US+ MPSoC Processing System - https://www.xilinx.com/support/documentation/ip_documentation/zynq_ultra_ps_e/v3_3/pg201-zynq-ultrascale-plus-processing-system.pdf
UG1209, Zynq US+ MPSoC: Embedded Design Tutorial - https://www.xilinx.com/support/documentation/sw_manuals/xilinx2020_1/ug1209-embedded-design-tutorial.pdf

We do not have specific reference designs for this but once you have created your board you can test this with a simple design with just a Zynq US+ MPSoC block dropped into IPI and configured the PS DDR and then export the XSA and run the memory test and Zynq US+ MPSoC DRAM Diagnostics test applications in SDK/Vitis. you can do this with nothing in PL logic and so there is no bitstream required. This is detailed in UG1209 which describes running a hello world application. All you need to do is run the memory tests instead after following this guide. PG201 can be used to see how to configure the PS DDR using an example for DDR3L but same theory applies.

-------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------

Kind regards,
Gareth

View solution in original post