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Explorer
Explorer
7,687 Views
Registered: ‎06-15-2010

32bit port ok, 64bit port failng: how to identify data error root cause?

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Hello!

 

We have a design with Spartan6, namely XC6SLX100T-3FGG676, with DDR2 memory attached, namely K4T51163QJ-BCE7, which is 32Mx16 part having total 512Mb and supporting DDR2-800 5-5-5. There are two chips at C3 and C4 controllers, but I am using only C3. Device is operating at extended performance conditions, memory clock speed is 400 MHz SDR. Our team had working with that for pretty long time in 6x32-bit port configuration. Someone says there was trouble with bidirectional functions, but once every port was used just one direction, there was no problems

 

Now I have created MIG design with just one 64-bit bidirectional port for C3. I see multiple data errors. If I write the sequence as :

00000000	01000000	02000000	03000000	
04000000 05000000 06000000 07000000 08000000 09000000 0A000000 0B000000
0C000000 0D000000 0E000000 0F000000 10000000 11000000 12000000 13000000
14000000 15000000 16000000 17000000 18000000 19000000 1A000000 1B000000
1C000000 1D000000 1E000000 1F000000

the values I read back are like

00000000	01000000	02000000	03000000	
04000000	05000000	06000000	07000000
08000000	09000800	0A000800	0B000800	
0C000800	0D000C00	0E000C00	0F000C00
10000C00	11000000	12000000	13000000	
14000000	15001400	16000000	17001400
18000000	19001800	1A000800	1B001800	
1C001800	1D001C00	1E001C00	1F001C00

I have groupped numbers in 32 bit, but in design they are read and written by 64. I have noticed, that odd quartes of data words have some kind of traces of the preceding even quartes. When I expect to read 0900_0000 I see 0900 is followed by 0800, so I it looks like bit #11 was 1 in the even quarter and errorneously latched again as 1 in the following odd quater, though expected to be 0.

 

If I put changing pattern to other side of the word, the situation is about the same. If I putt all zeros or all ones, they are read back properly, so the problem is definitely observed in switching.

 

As UG416 suggests, I have issued one write block and tried to read it multiple times. Once written, then errorneus data are read back corrupted same way. So, I guess, there is write issue.

 

Next I have tried to reduce memory clock from 400 MHz to 333 (DDR2-667), it seems to be working properly.

 

I'd like to ask for opinion on:

  1. What is a major difference between 32 and 64 bit ports operation, so one works fine while another fails?
  2. How do we identify the root cause of data error?

Thanks in advance

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Xilinx Employee
Xilinx Employee
13,610 Views
Registered: ‎07-11-2011

Hi,

 

There are few known issues in MCB with calibrated termination, it may cause data errors under certain scenarios listed in below AR.

http://www.xilinx.com/support/answers/36291.html

 

If the solutions provided in the AR do not suit to your board, I think you can go with unclaibrated termination, it should not cause any issue.

 

Hope this helps

 

-Vanitha

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Xilinx Employee
Xilinx Employee
7,671 Views
Registered: ‎07-11-2011

1.I do not notice any major differences between one X 64 bit port and 2 X32 bit port designs, there will be FIFOs but with different data widths, and the other difference could be round robin arbitration between among them.

2. If one works and the other do not, and as the errors are sensitive to frequnecy I suspect if SI is good, I would suggedt to cross check clock quality, if terminations are proper(try with calibrated, unclaibrated options) and verify supply voltages, RQ termination value etc.

 

Hope this helps

 

-Vanitha

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Explorer
Explorer
7,664 Views
Registered: ‎06-15-2010

Hello Vanitha,

 

I thought there might be some difference in access sequence. Like 32 bit port would require two acceccess to x16 device, while 64 bit port would require four. So one may imagine 32 bit access is in effect rising-falling access followed with pause(?) while 64 bit access takes four edges in line. That' speculation, of course, I am not that strong in physical layer.

 

What I did is tried your suggestion to change input pin termination to uncalibrated. And that helped. I do read back expected patterns repeatedly.

 

My knowledge on philosophy and life truth suggests, that extra efforts, like calibrated termination, should provide better result comparing to lazy options. However, in my case it seems that calibrated termination does not work well.

 

Could you please suggest, what to check about this situation?

 

Thanks in advance.

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Xilinx Employee
Xilinx Employee
13,611 Views
Registered: ‎07-11-2011

Hi,

 

There are few known issues in MCB with calibrated termination, it may cause data errors under certain scenarios listed in below AR.

http://www.xilinx.com/support/answers/36291.html

 

If the solutions provided in the AR do not suit to your board, I think you can go with unclaibrated termination, it should not cause any issue.

 

Hope this helps

 

-Vanitha

---------------------------------------------------------------------------------------------
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Mark the post - "Accept as solution" and give kudos if information provided is helpful and reply oriented

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Explorer
Explorer
7,655 Views
Registered: ‎06-15-2010

Hello,

 

Circuit designer reported to follow SP601, so all the conditions of above mentioned AR do apply. Perhaps I would try to play with reset timing later, but now will proceed with uncalibrated termination as it seems to solve my issue.

 

Thank you very much!

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Explorer
Explorer
7,567 Views
Registered: ‎06-15-2010

Just to close the case completely, I have tried to apply longer reset.

The refernce voltage network consists of two 20K resistors and 0.1uF capasitor. Equivalent Thevenin network has Re=10K. So the time constant of the network tau=ReC=10KOhm*0.1uF=1ms. To be sure, I would apply reset for at least 5*tau, i.e. 5ms. When I increased counter in reset network, it did help again.

So either way - uncalibrated input termination or calibrated with longer reset do the job.

Thanks again for pointing the solution.

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